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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_phase_det.vhd] - Blame information for rev 11

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----------------------------------------------------------------------
----                                                              ----
---- WISHBONE SPDIF IP Core                                       ----
----                                                              ----
---- This file is part of the SPDIF project                       ----
---- http://www.opencores.org/cores/spdif_interface/              ----
----                                                              ----
---- Description                                                  ----
---- Oversampling phase detector. Decodes bi-phase mark encoded   ----
---- signal. Clock must be at least 8 times higher than bit rate. ----
---- The SPDIF bitrate must be minimum 100kHz.                    ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
entity rx_phase_det is
  generic (WISH_BONE_FREQ: natural := 33);   -- WishBone frequency in MHz
  port (
    wb_clk_i: in std_logic;
    rxen: in std_logic;
    spdif: in std_logic;
    lock: out std_logic;
    rx_data: out std_logic;
    rx_data_en: out std_logic;
    rx_block_start: out std_logic;
    rx_frame_start: out std_logic;
    rx_channel_a: out std_logic;
    rx_error: out std_logic;
    ud_a_en: out std_logic;              -- user data ch. A enable
    ud_b_en: out std_logic;              -- user data ch. B enable
    cs_a_en: out std_logic;              -- channel status ch. A enable
    cs_b_en: out std_logic);             -- channel status ch. B enable);            
end rx_phase_det;
 
architecture rtl of rx_phase_det is
 
  constant TRANSITIONS : integer := 40;
  constant FRAMES_FOR_LOCK : integer := 3;
  signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISH_BONE_FREQ;
  signal last_cnt, max_thres : integer range 0 to 16 * WISH_BONE_FREQ;
  signal minpulse, minp, min_thres: integer range 0 to 8 * WISH_BONE_FREQ;
  signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
  signal trans_cnt : integer range 0 to TRANSITIONS;
  signal valid, p_long, p_short: std_logic;
  type pulse_type is (ZERO, SHORT, MED, LONG);
  type pulse_array is array (0 to 3) of pulse_type;
  signal preamble: pulse_array;
  signal new_pulse, short_idx, ilock: std_logic;
  type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX);
  signal framerx : frame_state;
  signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK;
  signal bit_cnt : integer range 0 to 63;
  signal pre_cnt : integer range 0 to 7;
  type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z);
  signal new_preamble, last_preamble : preamble_types;
  signal irx_channel_a : std_logic;
 
begin
 
  -- Pulse width analyzer
  PHDET: process (wb_clk_i, rxen)
  begin
    if rxen = '0' then            -- reset by configuration register bit
      maxpulse <= 0;
      maxp <= 0;
      mp_cnt <= 0;
      zspdif <= '0';
      zspdif_in <= '0';
      spdif_in <= '0';
      trans_cnt <= 0;
      minpulse <= 0;
      minp <= 0;
      last_cnt <= 0;
      trans <= '0';
      valid <= '0';
      preamble <= (ZERO, ZERO, ZERO, ZERO);
    else
      if rising_edge(wb_clk_i) then
        -- sync spdif signal to wishbone clock
        zspdif <= spdif;
        spdif_in <= zspdif;
        -- find the longest pulse, which is the bi-phase violation
        -- also find the shortest pulse
        zspdif_in <= spdif_in;
        if zspdif_in /= spdif_in then
          mp_cnt <= 0;
          trans <= '1';
          last_cnt <= mp_cnt;
          if mp_cnt > maxp then
            maxp <= mp_cnt;
          end if;
          if mp_cnt < minp then
            minp <= mp_cnt;
          end if;
        else
          trans <= '0';
          if mp_cnt < 16 * WISH_BONE_FREQ then
            mp_cnt <= mp_cnt + 1;
          end if;
        end if;
        -- transition counting
        if trans = '1' then
          if trans_cnt < TRANSITIONS then
            trans_cnt <= trans_cnt + 1;
          else
            -- the max/min pulse length is updated after given # of transitions
            trans_cnt <= 0;
            maxpulse <= maxp;
            maxp <= 0;
            minpulse <= minp;
            minp <= 8 * WISH_BONE_FREQ;
            min_thres <= maxp / 2;
            if maxp < 11 then
              max_thres <= maxp - 1;
            else
              max_thres <= maxp - 3;
            end if;
          end if;
        end if;
        -- detection of valid SPDIF signal
        if maxpulse > 6 then
          valid <= '1';
        else
          valid <= '0';
        end if;
        -- bit decoding
        if trans = '1' then
          if (last_cnt < min_thres) and (last_cnt > 0) then
            p_short <= '1';
            preamble(0) <= SHORT;
          else
            p_short <= '0';
          end if;
          if last_cnt >= max_thres then
            p_long <= '1';
            preamble(0) <= LONG;
          else
            p_long <= '0';
          end if;
          if last_cnt = 0 then
            preamble(0) <= ZERO;
          end if;
          if (last_cnt < max_thres) and (last_cnt >= min_thres) then
            preamble(0) <= MED;
          end if;
          preamble(3) <= preamble(2);
          preamble(2) <= preamble(1);
          preamble(1) <= preamble(0);
        end if;
        -- preamble detection
        if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT
          and preamble(0) = SHORT then
          new_preamble <= PRE_X;
        elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT
          and preamble(0) = MED then
          new_preamble <= PRE_Y;
        elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT
          and preamble(0) = LONG then
          new_preamble <= PRE_Z;
        else
          new_preamble <= NONE;
        end if;
        -- delayed transition pulse for the state machine
        ztrans <= trans;
        new_pulse <= ztrans;
      end if;
    end if;
  end process;
 
  lock <= ilock;
  rx_channel_a <= irx_channel_a;
 
  -- State machine that hunt for and lock onto sub-frames
  FRX: process (wb_clk_i, rxen)
  begin  -- process FRX
    if rxen = '0' then
      framerx <= IDLE;
      ilock <= '0';
      rx_data <= '0';
      rx_data_en <= '0';
      rx_block_start <= '0';
      rx_frame_start <= '0';
      irx_channel_a <= '0';
      ud_a_en <= '0';
      ud_b_en <= '0';
      cs_a_en <= '0';
      cs_b_en <= '0';
      rx_error <= '0';
    elsif rising_edge(wb_clk_i) then
      case framerx is
        when  IDLE =>                   -- wait for recevier to be enabled
          if valid = '1' then
            framerx <= HUNT;
          end if;
        when HUNT =>                    -- wait for preamble detection
          frame_cnt <= 0;
          ilock <= '0';
          rx_error <= '0';
          if new_pulse = '1' then
            if new_preamble /= NONE then
              framerx <= FRAMESTART;
            end if;
          end if;
        when FRAMESTART =>              -- reset sub-frame bit counter
          bit_cnt <= 0;
          pre_cnt <= 0;
          if frame_cnt < FRAMES_FOR_LOCK then
            frame_cnt <= frame_cnt + 1;
          else
            ilock <= '1';
          end if;
          last_preamble <= new_preamble;
          short_idx <= '0';
          rx_frame_start <= '1';
          rx_block_start <= '0';
          framerx <= FRAME_RX;
        when FRAME_RX =>                -- receive complete sub-frame
          if new_pulse = '1' then
            if bit_cnt < 28 then
              case preamble(0) is
                when ZERO =>
                  short_idx <= '0';
                when SHORT =>
                  if short_idx = '0' then
                    short_idx <= '1';
                  else
                    -- two short pulses is a logical '1'
                    bit_cnt <= bit_cnt + 1;
                    short_idx <= '0';
                    rx_data <= '1';
                    rx_data_en <= ilock;
                    -- user data enable for the capture register
                    if bit_cnt = 25 and ilock = '1' then
                      ud_a_en <= irx_channel_a;
                      ud_b_en <= not irx_channel_a;
                    end if;
                    -- channel status enable for the capture register
                    if bit_cnt = 26 and ilock = '1' then
                      cs_a_en <= irx_channel_a;
                      cs_b_en <= not irx_channel_a;
                    end if;
                  end if;
                when MED =>
                  -- medium pulse is logical '0'
                  bit_cnt <= bit_cnt + 1;
                  rx_data <= '0';
                  rx_data_en <= ilock;
                  short_idx <= '0';
                  -- user data enable for the capture register
                  if bit_cnt = 25 and ilock = '1' then
                    ud_a_en <= irx_channel_a;
                    ud_b_en <= not irx_channel_a;
                  end if;
                  -- channel status enable for the capture register
                  if bit_cnt = 26 and ilock = '1' then
                    cs_a_en <= irx_channel_a;
                    cs_b_en <= not irx_channel_a;
                  end if;
                when LONG =>
                  short_idx <= '0';
                when others =>
                  framerx <= HUNT;
              end case;
            else
              -- there should be 4 pulses in preamble
              if pre_cnt < 7 then
                pre_cnt <= pre_cnt + 1;
              else
                rx_error <= '1';
                framerx <= HUNT;
              end if;
              -- check for correct preamble here
              if pre_cnt = 3 then
                case last_preamble is
                  when PRE_X =>
                    if new_preamble = PRE_Y then
                      framerx <= FRAMESTART;
                      irx_channel_a <= '0';
                    else
                      rx_error <= '1';
                      framerx <= HUNT;
                    end if;
                  when PRE_Y =>
                    if new_preamble = PRE_X or new_preamble = PRE_Z then
                      irx_channel_a <= '1';
                      -- start of new block?
                      if new_preamble = PRE_Z then
                        rx_block_start <= '1';
                      end if;
                      framerx <= FRAMESTART;
                    else
                      rx_error <= '1';
                      framerx <= HUNT;
                    end if;
                  when PRE_Z =>
                    if new_preamble = PRE_Y then
                      irx_channel_a <= '0';
                      framerx <= FRAMESTART;
                    else
                      rx_error <= '1';
                      framerx <= HUNT;
                    end if;
                  when others =>
                    rx_error <= '1';
                    framerx <= HUNT;
                end case;
              end if;
            end if;
          else
            rx_data_en <= '0';
            rx_block_start <= '0';
            rx_frame_start <= '0';
            ud_a_en <= '0';
            ud_b_en <= '0';
            cs_a_en <= '0';
            cs_b_en <= '0';
          end if;
        when others =>
          framerx <= IDLE;
      end case;
    end if;
  end process FRX;
 
end rtl;

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Subversion Repositories spdif_interface

[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_phase_det.vhd] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	gedra	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE SPDIF IP Core ----`
4			`---- ----`
5			`---- This file is part of the SPDIF project ----`
6			`---- http://www.opencores.org/cores/spdif_interface/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Oversampling phase detector. Decodes bi-phase mark encoded ----`
10			`---- signal. Clock must be at least 8 times higher than bit rate. ----`
11			`---- The SPDIF bitrate must be minimum 100kHz. ----`
12			`---- ----`
13			`---- To Do: ----`
14			`---- - ----`
15			`---- ----`
16			`---- Author(s): ----`
17			`---- - Geir Drange, gedra@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2004 Authors and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45			`--`
46			`-- CVS Revision History`
47			`--`
48			`-- $Log: not supported by cvs2svn $`
49			`--`
50
51			`LIBRARY ieee;`
52			`USE ieee.std_logic_1164.ALL;`
53
54			`entity rx_phase_det is`
55			`generic (WISH_BONE_FREQ: natural := 33); -- WishBone frequency in MHz`
56			`port (`
57			`wb_clk_i: in std_logic;`
58			`rxen: in std_logic;`
59			`spdif: in std_logic;`
60			`lock: out std_logic;`
61			`rx_data: out std_logic;`
62			`rx_data_en: out std_logic;`
63			`rx_block_start: out std_logic;`
64			`rx_frame_start: out std_logic;`
65			`rx_channel_a: out std_logic;`
66			`rx_error: out std_logic;`
67			`ud_a_en: out std_logic; -- user data ch. A enable`
68			`ud_b_en: out std_logic; -- user data ch. B enable`
69			`cs_a_en: out std_logic; -- channel status ch. A enable`
70			`cs_b_en: out std_logic); -- channel status ch. B enable);`
71			`end rx_phase_det;`
72
73			`architecture rtl of rx_phase_det is`
74
75			`constant TRANSITIONS : integer := 40;`
76			`constant FRAMES_FOR_LOCK : integer := 3;`
77			`signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISH_BONE_FREQ;`
78			`signal last_cnt, max_thres : integer range 0 to 16 * WISH_BONE_FREQ;`
79			`signal minpulse, minp, min_thres: integer range 0 to 8 * WISH_BONE_FREQ;`
80			`signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;`
81			`signal trans_cnt : integer range 0 to TRANSITIONS;`
82			`signal valid, p_long, p_short: std_logic;`
83			`type pulse_type is (ZERO, SHORT, MED, LONG);`
84			`type pulse_array is array (0 to 3) of pulse_type;`
85			`signal preamble: pulse_array;`
86			`signal new_pulse, short_idx, ilock: std_logic;`
87			`type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX);`
88			`signal framerx : frame_state;`
89			`signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK;`
90			`signal bit_cnt : integer range 0 to 63;`
91			`signal pre_cnt : integer range 0 to 7;`
92			`type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z);`
93			`signal new_preamble, last_preamble : preamble_types;`
94			`signal irx_channel_a : std_logic;`
95
96			`begin`
97
98			`-- Pulse width analyzer`
99			`PHDET: process (wb_clk_i, rxen)`
100			`begin`
101			`if rxen = '0' then -- reset by configuration register bit`
102			`maxpulse <= 0;`
103			`maxp <= 0;`
104			`mp_cnt <= 0;`
105			`zspdif <= '0';`
106			`zspdif_in <= '0';`
107			`spdif_in <= '0';`
108			`trans_cnt <= 0;`
109			`minpulse <= 0;`
110			`minp <= 0;`
111			`last_cnt <= 0;`
112			`trans <= '0';`
113			`valid <= '0';`
114			`preamble <= (ZERO, ZERO, ZERO, ZERO);`
115			`else`
116			`if rising_edge(wb_clk_i) then`
117			`-- sync spdif signal to wishbone clock`
118			`zspdif <= spdif;`
119			`spdif_in <= zspdif;`
120			`-- find the longest pulse, which is the bi-phase violation`
121			`-- also find the shortest pulse`
122			`zspdif_in <= spdif_in;`
123			`if zspdif_in /= spdif_in then`
124			`mp_cnt <= 0;`
125			`trans <= '1';`
126			`last_cnt <= mp_cnt;`
127			`if mp_cnt > maxp then`
128			`maxp <= mp_cnt;`
129			`end if;`
130			`if mp_cnt < minp then`
131			`minp <= mp_cnt;`
132			`end if;`
133			`else`
134			`trans <= '0';`
135			`if mp_cnt < 16 * WISH_BONE_FREQ then`
136			`mp_cnt <= mp_cnt + 1;`
137			`end if;`
138			`end if;`
139			`-- transition counting`
140			`if trans = '1' then`
141			`if trans_cnt < TRANSITIONS then`
142			`trans_cnt <= trans_cnt + 1;`
143			`else`
144			`-- the max/min pulse length is updated after given # of transitions`
145			`trans_cnt <= 0;`
146			`maxpulse <= maxp;`
147			`maxp <= 0;`
148			`minpulse <= minp;`
149			`minp <= 8 * WISH_BONE_FREQ;`
150			`min_thres <= maxp / 2;`
151			`if maxp < 11 then`
152			`max_thres <= maxp - 1;`
153			`else`
154			`max_thres <= maxp - 3;`
155			`end if;`
156			`end if;`
157			`end if;`
158			`-- detection of valid SPDIF signal`
159			`if maxpulse > 6 then`
160			`valid <= '1';`
161			`else`
162			`valid <= '0';`
163			`end if;`
164			`-- bit decoding`
165			`if trans = '1' then`
166			`if (last_cnt < min_thres) and (last_cnt > 0) then`
167			`p_short <= '1';`
168			`preamble(0) <= SHORT;`
169			`else`
170			`p_short <= '0';`
171			`end if;`
172			`if last_cnt >= max_thres then`
173			`p_long <= '1';`
174			`preamble(0) <= LONG;`
175			`else`
176			`p_long <= '0';`
177			`end if;`
178			`if last_cnt = 0 then`
179			`preamble(0) <= ZERO;`
180			`end if;`
181			`if (last_cnt < max_thres) and (last_cnt >= min_thres) then`
182			`preamble(0) <= MED;`
183			`end if;`
184			`preamble(3) <= preamble(2);`
185			`preamble(2) <= preamble(1);`
186			`preamble(1) <= preamble(0);`
187			`end if;`
188			`-- preamble detection`
189			`if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT`
190			`and preamble(0) = SHORT then`
191			`new_preamble <= PRE_X;`
192			`elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT`
193			`and preamble(0) = MED then`
194			`new_preamble <= PRE_Y;`
195			`elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT`
196			`and preamble(0) = LONG then`
197			`new_preamble <= PRE_Z;`
198			`else`
199			`new_preamble <= NONE;`
200			`end if;`
201			`-- delayed transition pulse for the state machine`
202			`ztrans <= trans;`
203			`new_pulse <= ztrans;`
204			`end if;`
205			`end if;`
206			`end process;`
207
208			`lock <= ilock;`
209			`rx_channel_a <= irx_channel_a;`
210
211			`-- State machine that hunt for and lock onto sub-frames`
212			`FRX: process (wb_clk_i, rxen)`
213			`begin -- process FRX`
214			`if rxen = '0' then`
215			`framerx <= IDLE;`
216			`ilock <= '0';`
217			`rx_data <= '0';`
218			`rx_data_en <= '0';`
219			`rx_block_start <= '0';`
220			`rx_frame_start <= '0';`
221			`irx_channel_a <= '0';`
222			`ud_a_en <= '0';`
223			`ud_b_en <= '0';`
224			`cs_a_en <= '0';`
225			`cs_b_en <= '0';`
226			`rx_error <= '0';`
227			`elsif rising_edge(wb_clk_i) then`
228			`case framerx is`
229			`when IDLE => -- wait for recevier to be enabled`
230			`if valid = '1' then`
231			`framerx <= HUNT;`
232			`end if;`
233			`when HUNT => -- wait for preamble detection`
234			`frame_cnt <= 0;`
235			`ilock <= '0';`
236			`rx_error <= '0';`
237			`if new_pulse = '1' then`
238			`if new_preamble /= NONE then`
239			`framerx <= FRAMESTART;`
240			`end if;`
241			`end if;`
242			`when FRAMESTART => -- reset sub-frame bit counter`
243			`bit_cnt <= 0;`
244			`pre_cnt <= 0;`
245			`if frame_cnt < FRAMES_FOR_LOCK then`
246			`frame_cnt <= frame_cnt + 1;`
247			`else`
248			`ilock <= '1';`
249			`end if;`
250			`last_preamble <= new_preamble;`
251			`short_idx <= '0';`
252			`rx_frame_start <= '1';`
253			`rx_block_start <= '0';`
254			`framerx <= FRAME_RX;`
255			`when FRAME_RX => -- receive complete sub-frame`
256			`if new_pulse = '1' then`
257			`if bit_cnt < 28 then`
258			`case preamble(0) is`
259			`when ZERO =>`
260			`short_idx <= '0';`
261			`when SHORT =>`
262			`if short_idx = '0' then`
263			`short_idx <= '1';`
264			`else`
265			`-- two short pulses is a logical '1'`
266			`bit_cnt <= bit_cnt + 1;`
267			`short_idx <= '0';`
268			`rx_data <= '1';`
269			`rx_data_en <= ilock;`
270			`-- user data enable for the capture register`
271			`if bit_cnt = 25 and ilock = '1' then`
272			`ud_a_en <= irx_channel_a;`
273			`ud_b_en <= not irx_channel_a;`
274			`end if;`
275			`-- channel status enable for the capture register`
276			`if bit_cnt = 26 and ilock = '1' then`
277			`cs_a_en <= irx_channel_a;`
278			`cs_b_en <= not irx_channel_a;`
279			`end if;`
280			`end if;`
281			`when MED =>`
282			`-- medium pulse is logical '0'`
283			`bit_cnt <= bit_cnt + 1;`
284			`rx_data <= '0';`
285			`rx_data_en <= ilock;`
286			`short_idx <= '0';`
287			`-- user data enable for the capture register`
288			`if bit_cnt = 25 and ilock = '1' then`
289			`ud_a_en <= irx_channel_a;`
290			`ud_b_en <= not irx_channel_a;`
291			`end if;`
292			`-- channel status enable for the capture register`
293			`if bit_cnt = 26 and ilock = '1' then`
294			`cs_a_en <= irx_channel_a;`
295			`cs_b_en <= not irx_channel_a;`
296			`end if;`
297			`when LONG =>`
298			`short_idx <= '0';`
299			`when others =>`
300			`framerx <= HUNT;`
301			`end case;`
302			`else`
303			`-- there should be 4 pulses in preamble`
304			`if pre_cnt < 7 then`
305			`pre_cnt <= pre_cnt + 1;`
306			`else`
307			`rx_error <= '1';`
308			`framerx <= HUNT;`
309			`end if;`
310			`-- check for correct preamble here`
311			`if pre_cnt = 3 then`
312			`case last_preamble is`
313			`when PRE_X =>`
314			`if new_preamble = PRE_Y then`
315			`framerx <= FRAMESTART;`
316			`irx_channel_a <= '0';`
317			`else`
318			`rx_error <= '1';`
319			`framerx <= HUNT;`
320			`end if;`
321			`when PRE_Y =>`
322			`if new_preamble = PRE_X or new_preamble = PRE_Z then`
323			`irx_channel_a <= '1';`
324			`-- start of new block?`
325			`if new_preamble = PRE_Z then`
326			`rx_block_start <= '1';`
327			`end if;`
328			`framerx <= FRAMESTART;`
329			`else`
330			`rx_error <= '1';`
331			`framerx <= HUNT;`
332			`end if;`
333			`when PRE_Z =>`
334			`if new_preamble = PRE_Y then`
335			`irx_channel_a <= '0';`
336			`framerx <= FRAMESTART;`
337			`else`
338			`rx_error <= '1';`
339			`framerx <= HUNT;`
340			`end if;`
341			`when others =>`
342			`rx_error <= '1';`
343			`framerx <= HUNT;`
344			`end case;`
345			`end if;`
346			`end if;`
347			`else`
348			`rx_data_en <= '0';`
349			`rx_block_start <= '0';`
350			`rx_frame_start <= '0';`
351			`ud_a_en <= '0';`
352			`ud_b_en <= '0';`
353			`cs_a_en <= '0';`
354			`cs_b_en <= '0';`
355			`end if;`
356			`when others =>`
357			`framerx <= IDLE;`
358			`end case;`
359			`end if;`
360			`end process FRX;`
361
362			`end rtl;`