URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_phase_det.vhd] - Blame information for rev 20

Go to most recent revision | Details | Compare with Previous | View Log


----------------------------------------------------------------------
----                                                              ----
---- WISHBONE SPDIF IP Core                                       ----
----                                                              ----
---- This file is part of the SPDIF project                       ----
---- http://www.opencores.org/cores/spdif_interface/              ----
----                                                              ----
---- Description                                                  ----
---- Oversampling phase detector. Decodes bi-phase mark encoded   ----
---- signal. Clock must be at least 8 times higher than bit rate. ----
---- The SPDIF bitrate must be minimum 100kHz.                    ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.1  2004/06/06 15:43:02  gedra
-- Early version of the bi-phase mark decoder.
--
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity rx_phase_det is
  generic (WISHBONE_FREQ: natural := 33);   -- WishBone frequency in MHz
  port (
    wb_clk_i: in std_logic;             -- wishbone clock
    rxen: in std_logic;                 -- phase detector enable
    spdif: in std_logic;                -- SPDIF input signal
    lock: out std_logic;                -- true if locked to spdif input
    rx_data: out std_logic;             -- recevied data
    rx_data_en: out std_logic;          -- received data enable
    rx_block_start: out std_logic;      -- start-of-block pulse
    rx_frame_start: out std_logic;      -- start-of-frame pulse
    rx_channel_a: out std_logic;        -- 1 if channel A frame is recevied
    rx_error: out std_logic;            -- signal error was detected
    ud_a_en: out std_logic;             -- user data ch. A enable
    ud_b_en: out std_logic;             -- user data ch. B enable
    cs_a_en: out std_logic;             -- channel status ch. A enable
    cs_b_en: out std_logic);            -- channel status ch. B enable);            
end rx_phase_det;
 
architecture rtl of rx_phase_det is
 
  constant TRANSITIONS : integer := 40;
  constant FRAMES_FOR_LOCK : integer := 3;
  signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISHBONE_FREQ;
  signal last_cnt, max_thres : integer range 0 to 16 * WISHBONE_FREQ;
  signal minpulse, minp, min_thres: integer range 0 to 8 * WISHBONE_FREQ;
  signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;
  signal trans_cnt : integer range 0 to TRANSITIONS;
  signal valid, p_long, p_short: std_logic;
  type pulse_type is (ZERO, SHORT, MED, LONG);
  type pulse_array is array (0 to 3) of pulse_type;
  signal preamble: pulse_array;
  signal new_pulse, short_idx, ilock: std_logic;
  type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX);
  signal framerx : frame_state;
  signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK;
  signal bit_cnt : integer range 0 to 63;
  signal pre_cnt : integer range 0 to 7;
  type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z);
  signal new_preamble, last_preamble : preamble_types;
  signal irx_channel_a : std_logic;
 
begin
 
  -- Pulse width analyzer
  PHDET: process (wb_clk_i, rxen)
  begin
    if rxen = '0' then            -- reset by configuration register bit
      maxpulse <= 0;
      maxp <= 0;
      mp_cnt <= 0;
      zspdif <= '0';
      zspdif_in <= '0';
      spdif_in <= '0';
      trans_cnt <= 0;
      minpulse <= 0;
      minp <= 0;
      last_cnt <= 0;
      trans <= '0';
      valid <= '0';
      preamble <= (ZERO, ZERO, ZERO, ZERO);
    else
      if rising_edge(wb_clk_i) then
        -- sync spdif signal to wishbone clock
        zspdif <= spdif;
        spdif_in <= zspdif;
        -- find the longest pulse, which is the bi-phase violation
        -- also find the shortest pulse
        zspdif_in <= spdif_in;
        if zspdif_in /= spdif_in then
          mp_cnt <= 0;
          trans <= '1';
          last_cnt <= mp_cnt;
          if mp_cnt > maxp then
            maxp <= mp_cnt;
          end if;
          if mp_cnt < minp then
            minp <= mp_cnt;
          end if;
        else
          trans <= '0';
          if mp_cnt < 16 * WISHBONE_FREQ then
            mp_cnt <= mp_cnt + 1;
          end if;
        end if;
        -- transition counting
        if trans = '1' then
          if trans_cnt < TRANSITIONS then
            trans_cnt <= trans_cnt + 1;
          else
            -- the max/min pulse length is updated after given # of transitions
            trans_cnt <= 0;
            maxpulse <= maxp;
            maxp <= 0;
            minpulse <= minp;
            minp <= 8 * WISHBONE_FREQ;
            min_thres <= maxp / 2;
            if maxp < 11 then
              max_thres <= maxp - 1;
            else
              max_thres <= maxp - 3;
            end if;
          end if;
        end if;
        -- detection of valid SPDIF signal
        if maxpulse > 6 then
          valid <= '1';
        else
          valid <= '0';
        end if;
        -- bit decoding
        if trans = '1' then
          if (last_cnt < min_thres) and (last_cnt > 0) then
            p_short <= '1';
            preamble(0) <= SHORT;
          else
            p_short <= '0';
          end if;
          if last_cnt >= max_thres then
            p_long <= '1';
            preamble(0) <= LONG;
          else
            p_long <= '0';
          end if;
          if last_cnt = 0 then
            preamble(0) <= ZERO;
          end if;
          if (last_cnt < max_thres) and (last_cnt >= min_thres) then
            preamble(0) <= MED;
          end if;
          preamble(3) <= preamble(2);
          preamble(2) <= preamble(1);
          preamble(1) <= preamble(0);
        end if;
        -- preamble detection
        if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT
          and preamble(0) = SHORT then
          new_preamble <= PRE_X;
        elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT
          and preamble(0) = MED then
          new_preamble <= PRE_Y;
        elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT
          and preamble(0) = LONG then
          new_preamble <= PRE_Z;
        else
          new_preamble <= NONE;
        end if;
        -- delayed transition pulse for the state machine
        ztrans <= trans;
        new_pulse <= ztrans;
      end if;
    end if;
  end process;
 
  lock <= ilock;
  rx_channel_a <= irx_channel_a;
 
  -- State machine that hunt for and lock onto sub-frames
  FRX: process (wb_clk_i, rxen)
  begin  -- process FRX
    if rxen = '0' then
      framerx <= IDLE;
      ilock <= '0';
      rx_data <= '0';
      rx_data_en <= '0';
      rx_block_start <= '0';
      rx_frame_start <= '0';
      irx_channel_a <= '0';
      ud_a_en <= '0';
      ud_b_en <= '0';
      cs_a_en <= '0';
      cs_b_en <= '0';
      rx_error <= '0';
    elsif rising_edge(wb_clk_i) then
      case framerx is
        when  IDLE =>                   -- wait for recevier to be enabled
          if valid = '1' then
            framerx <= HUNT;
          end if;
        when HUNT =>                    -- wait for preamble detection
          frame_cnt <= 0;
          ilock <= '0';
          rx_error <= '0';
          if new_pulse = '1' then
            if new_preamble /= NONE then
              framerx <= FRAMESTART;
            end if;
          end if;
        when FRAMESTART =>              -- reset sub-frame bit counter
          bit_cnt <= 0;
          pre_cnt <= 0;
          if frame_cnt < FRAMES_FOR_LOCK then
            frame_cnt <= frame_cnt + 1;
          else
            ilock <= '1';
          end if;
          last_preamble <= new_preamble;
          short_idx <= '0';
          rx_frame_start <= '1';
          rx_block_start <= '0';
          framerx <= FRAME_RX;
        when FRAME_RX =>                -- receive complete sub-frame
          if new_pulse = '1' then
            if bit_cnt < 28 then
              case preamble(0) is
                when ZERO =>
                  short_idx <= '0';
                when SHORT =>
                  if short_idx = '0' then
                    short_idx <= '1';
                  else
                    -- two short pulses is a logical '1'
                    bit_cnt <= bit_cnt + 1;
                    short_idx <= '0';
                    rx_data <= '1';
                    rx_data_en <= ilock;
                    -- user data enable for the capture register
                    if bit_cnt = 25 and ilock = '1' then
                      ud_a_en <= irx_channel_a;
                      ud_b_en <= not irx_channel_a;
                    end if;
                    -- channel status enable for the capture register
                    if bit_cnt = 26 and ilock = '1' then
                      cs_a_en <= irx_channel_a;
                      cs_b_en <= not irx_channel_a;
                    end if;
                  end if;
                when MED =>
                  -- medium pulse is logical '0'
                  bit_cnt <= bit_cnt + 1;
                  rx_data <= '0';
                  rx_data_en <= ilock;
                  short_idx <= '0';
                  -- user data enable for the capture register
                  if bit_cnt = 25 and ilock = '1' then
                    ud_a_en <= irx_channel_a;
                    ud_b_en <= not irx_channel_a;
                  end if;
                  -- channel status enable for the capture register
                  if bit_cnt = 26 and ilock = '1' then
                    cs_a_en <= irx_channel_a;
                    cs_b_en <= not irx_channel_a;
                  end if;
                when LONG =>
                  short_idx <= '0';
                when others =>
                  framerx <= HUNT;
              end case;
            else
              -- there should be 4 pulses in preamble
              if pre_cnt < 7 then
                pre_cnt <= pre_cnt + 1;
              else
                rx_error <= '1';
                framerx <= HUNT;
              end if;
              -- check for correct preamble here
              if pre_cnt = 3 then
                case last_preamble is
                  when PRE_X =>
                    if new_preamble = PRE_Y then
                      framerx <= FRAMESTART;
                      irx_channel_a <= '0';
                    else
                      rx_error <= '1';
                      framerx <= HUNT;
                    end if;
                  when PRE_Y =>
                    if new_preamble = PRE_X or new_preamble = PRE_Z then
                      irx_channel_a <= '1';
                      -- start of new block?
                      if new_preamble = PRE_Z then
                        rx_block_start <= '1';
                      end if;
                      framerx <= FRAMESTART;
                    else
                      rx_error <= '1';
                      framerx <= HUNT;
                    end if;
                  when PRE_Z =>
                    if new_preamble = PRE_Y then
                      irx_channel_a <= '0';
                      framerx <= FRAMESTART;
                    else
                      rx_error <= '1';
                      framerx <= HUNT;
                    end if;
                  when others =>
                    rx_error <= '1';
                    framerx <= HUNT;
                end case;
              end if;
            end if;
          else
            rx_data_en <= '0';
            rx_block_start <= '0';
            rx_frame_start <= '0';
            ud_a_en <= '0';
            ud_b_en <= '0';
            cs_a_en <= '0';
            cs_b_en <= '0';
          end if;
        when others =>
          framerx <= IDLE;
      end case;
    end if;
  end process FRX;
 
end rtl;

Line No.	Rev	Author	Line
1	11	gedra	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE SPDIF IP Core ----`
4			`---- ----`
5			`---- This file is part of the SPDIF project ----`
6			`---- http://www.opencores.org/cores/spdif_interface/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- Oversampling phase detector. Decodes bi-phase mark encoded ----`
10			`---- signal. Clock must be at least 8 times higher than bit rate. ----`
11			`---- The SPDIF bitrate must be minimum 100kHz. ----`
12			`---- ----`
13			`---- To Do: ----`
14			`---- - ----`
15			`---- ----`
16			`---- Author(s): ----`
17			`---- - Geir Drange, gedra@opencores.org ----`
18			`---- ----`
19			`----------------------------------------------------------------------`
20			`---- ----`
21			`---- Copyright (C) 2004 Authors and OPENCORES.ORG ----`
22			`---- ----`
23			`---- This source file may be used and distributed without ----`
24			`---- restriction provided that this copyright statement is not ----`
25			`---- removed from the file and that any derivative work contains ----`
26			`---- the original copyright notice and the associated disclaimer. ----`
27			`---- ----`
28			`---- This source file is free software; you can redistribute it ----`
29			`---- and/or modify it under the terms of the GNU Lesser General ----`
30			`---- Public License as published by the Free Software Foundation; ----`
31			`---- either version 2.1 of the License, or (at your option) any ----`
32			`---- later version. ----`
33			`---- ----`
34			`---- This source is distributed in the hope that it will be ----`
35			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
36			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
37			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
38			`---- details. ----`
39			`---- ----`
40			`---- You should have received a copy of the GNU Lesser General ----`
41			`---- Public License along with this source; if not, download it ----`
42			`---- from http://www.opencores.org/lgpl.shtml ----`
43			`---- ----`
44			`----------------------------------------------------------------------`
45			`--`
46			`-- CVS Revision History`
47			`--`
48			`-- $Log: not supported by cvs2svn $`
49	20	gedra	`-- Revision 1.1 2004/06/06 15:43:02 gedra`
50			`-- Early version of the bi-phase mark decoder.`
51	11	gedra	`--`
52	20	gedra	`--`
53	11	gedra
54	20	gedra	`library ieee;`
55			`use ieee.std_logic_1164.all;`
56	11	gedra
57			`entity rx_phase_det is`
58	20	gedra	`generic (WISHBONE_FREQ: natural := 33); -- WishBone frequency in MHz`
59	11	gedra	`port (`
60	20	gedra	`wb_clk_i: in std_logic; -- wishbone clock`
61			`rxen: in std_logic; -- phase detector enable`
62			`spdif: in std_logic; -- SPDIF input signal`
63			`lock: out std_logic; -- true if locked to spdif input`
64			`rx_data: out std_logic; -- recevied data`
65			`rx_data_en: out std_logic; -- received data enable`
66			`rx_block_start: out std_logic; -- start-of-block pulse`
67			`rx_frame_start: out std_logic; -- start-of-frame pulse`
68			`rx_channel_a: out std_logic; -- 1 if channel A frame is recevied`
69			`rx_error: out std_logic; -- signal error was detected`
70			`ud_a_en: out std_logic; -- user data ch. A enable`
71			`ud_b_en: out std_logic; -- user data ch. B enable`
72			`cs_a_en: out std_logic; -- channel status ch. A enable`
73			`cs_b_en: out std_logic); -- channel status ch. B enable);`
74	11	gedra	`end rx_phase_det;`
75
76			`architecture rtl of rx_phase_det is`
77
78			`constant TRANSITIONS : integer := 40;`
79			`constant FRAMES_FOR_LOCK : integer := 3;`
80	20	gedra	`signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * WISHBONE_FREQ;`
81			`signal last_cnt, max_thres : integer range 0 to 16 * WISHBONE_FREQ;`
82			`signal minpulse, minp, min_thres: integer range 0 to 8 * WISHBONE_FREQ;`
83	11	gedra	`signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic;`
84			`signal trans_cnt : integer range 0 to TRANSITIONS;`
85			`signal valid, p_long, p_short: std_logic;`
86			`type pulse_type is (ZERO, SHORT, MED, LONG);`
87			`type pulse_array is array (0 to 3) of pulse_type;`
88			`signal preamble: pulse_array;`
89			`signal new_pulse, short_idx, ilock: std_logic;`
90			`type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX);`
91			`signal framerx : frame_state;`
92			`signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK;`
93			`signal bit_cnt : integer range 0 to 63;`
94			`signal pre_cnt : integer range 0 to 7;`
95			`type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z);`
96			`signal new_preamble, last_preamble : preamble_types;`
97			`signal irx_channel_a : std_logic;`
98
99			`begin`
100
101			`-- Pulse width analyzer`
102			`PHDET: process (wb_clk_i, rxen)`
103			`begin`
104			`if rxen = '0' then -- reset by configuration register bit`
105			`maxpulse <= 0;`
106			`maxp <= 0;`
107			`mp_cnt <= 0;`
108			`zspdif <= '0';`
109			`zspdif_in <= '0';`
110			`spdif_in <= '0';`
111			`trans_cnt <= 0;`
112			`minpulse <= 0;`
113			`minp <= 0;`
114			`last_cnt <= 0;`
115			`trans <= '0';`
116			`valid <= '0';`
117			`preamble <= (ZERO, ZERO, ZERO, ZERO);`
118			`else`
119			`if rising_edge(wb_clk_i) then`
120			`-- sync spdif signal to wishbone clock`
121			`zspdif <= spdif;`
122			`spdif_in <= zspdif;`
123			`-- find the longest pulse, which is the bi-phase violation`
124			`-- also find the shortest pulse`
125			`zspdif_in <= spdif_in;`
126			`if zspdif_in /= spdif_in then`
127			`mp_cnt <= 0;`
128			`trans <= '1';`
129			`last_cnt <= mp_cnt;`
130			`if mp_cnt > maxp then`
131			`maxp <= mp_cnt;`
132			`end if;`
133			`if mp_cnt < minp then`
134			`minp <= mp_cnt;`
135			`end if;`
136			`else`
137			`trans <= '0';`
138	20	gedra	`if mp_cnt < 16 * WISHBONE_FREQ then`
139	11	gedra	`mp_cnt <= mp_cnt + 1;`
140			`end if;`
141			`end if;`
142			`-- transition counting`
143			`if trans = '1' then`
144			`if trans_cnt < TRANSITIONS then`
145			`trans_cnt <= trans_cnt + 1;`
146			`else`
147			`-- the max/min pulse length is updated after given # of transitions`
148			`trans_cnt <= 0;`
149			`maxpulse <= maxp;`
150			`maxp <= 0;`
151			`minpulse <= minp;`
152	20	gedra	`minp <= 8 * WISHBONE_FREQ;`
153	11	gedra	`min_thres <= maxp / 2;`
154			`if maxp < 11 then`
155			`max_thres <= maxp - 1;`
156			`else`
157			`max_thres <= maxp - 3;`
158			`end if;`
159			`end if;`
160			`end if;`
161			`-- detection of valid SPDIF signal`
162			`if maxpulse > 6 then`
163			`valid <= '1';`
164			`else`
165			`valid <= '0';`
166			`end if;`
167			`-- bit decoding`
168			`if trans = '1' then`
169			`if (last_cnt < min_thres) and (last_cnt > 0) then`
170			`p_short <= '1';`
171			`preamble(0) <= SHORT;`
172			`else`
173			`p_short <= '0';`
174			`end if;`
175			`if last_cnt >= max_thres then`
176			`p_long <= '1';`
177			`preamble(0) <= LONG;`
178			`else`
179			`p_long <= '0';`
180			`end if;`
181			`if last_cnt = 0 then`
182			`preamble(0) <= ZERO;`
183			`end if;`
184			`if (last_cnt < max_thres) and (last_cnt >= min_thres) then`
185			`preamble(0) <= MED;`
186			`end if;`
187			`preamble(3) <= preamble(2);`
188			`preamble(2) <= preamble(1);`
189			`preamble(1) <= preamble(0);`
190			`end if;`
191			`-- preamble detection`
192			`if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT`
193			`and preamble(0) = SHORT then`
194			`new_preamble <= PRE_X;`
195			`elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT`
196			`and preamble(0) = MED then`
197			`new_preamble <= PRE_Y;`
198			`elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT`
199			`and preamble(0) = LONG then`
200			`new_preamble <= PRE_Z;`
201			`else`
202			`new_preamble <= NONE;`
203			`end if;`
204			`-- delayed transition pulse for the state machine`
205			`ztrans <= trans;`
206			`new_pulse <= ztrans;`
207			`end if;`
208			`end if;`
209			`end process;`
210
211			`lock <= ilock;`
212			`rx_channel_a <= irx_channel_a;`
213
214			`-- State machine that hunt for and lock onto sub-frames`
215			`FRX: process (wb_clk_i, rxen)`
216			`begin -- process FRX`
217			`if rxen = '0' then`
218			`framerx <= IDLE;`
219			`ilock <= '0';`
220			`rx_data <= '0';`
221			`rx_data_en <= '0';`
222			`rx_block_start <= '0';`
223			`rx_frame_start <= '0';`
224			`irx_channel_a <= '0';`
225			`ud_a_en <= '0';`
226			`ud_b_en <= '0';`
227			`cs_a_en <= '0';`
228			`cs_b_en <= '0';`
229			`rx_error <= '0';`
230			`elsif rising_edge(wb_clk_i) then`
231			`case framerx is`
232			`when IDLE => -- wait for recevier to be enabled`
233			`if valid = '1' then`
234			`framerx <= HUNT;`
235			`end if;`
236			`when HUNT => -- wait for preamble detection`
237			`frame_cnt <= 0;`
238			`ilock <= '0';`
239			`rx_error <= '0';`
240			`if new_pulse = '1' then`
241			`if new_preamble /= NONE then`
242			`framerx <= FRAMESTART;`
243			`end if;`
244			`end if;`
245			`when FRAMESTART => -- reset sub-frame bit counter`
246			`bit_cnt <= 0;`
247			`pre_cnt <= 0;`
248			`if frame_cnt < FRAMES_FOR_LOCK then`
249			`frame_cnt <= frame_cnt + 1;`
250			`else`
251			`ilock <= '1';`
252			`end if;`
253			`last_preamble <= new_preamble;`
254			`short_idx <= '0';`
255			`rx_frame_start <= '1';`
256			`rx_block_start <= '0';`
257			`framerx <= FRAME_RX;`
258			`when FRAME_RX => -- receive complete sub-frame`
259			`if new_pulse = '1' then`
260			`if bit_cnt < 28 then`
261			`case preamble(0) is`
262			`when ZERO =>`
263			`short_idx <= '0';`
264			`when SHORT =>`
265			`if short_idx = '0' then`
266			`short_idx <= '1';`
267			`else`
268			`-- two short pulses is a logical '1'`
269			`bit_cnt <= bit_cnt + 1;`
270			`short_idx <= '0';`
271			`rx_data <= '1';`
272			`rx_data_en <= ilock;`
273			`-- user data enable for the capture register`
274			`if bit_cnt = 25 and ilock = '1' then`
275			`ud_a_en <= irx_channel_a;`
276			`ud_b_en <= not irx_channel_a;`
277			`end if;`
278			`-- channel status enable for the capture register`
279			`if bit_cnt = 26 and ilock = '1' then`
280			`cs_a_en <= irx_channel_a;`
281			`cs_b_en <= not irx_channel_a;`
282			`end if;`
283			`end if;`
284			`when MED =>`
285			`-- medium pulse is logical '0'`
286			`bit_cnt <= bit_cnt + 1;`
287			`rx_data <= '0';`
288			`rx_data_en <= ilock;`
289			`short_idx <= '0';`
290			`-- user data enable for the capture register`
291			`if bit_cnt = 25 and ilock = '1' then`
292			`ud_a_en <= irx_channel_a;`
293			`ud_b_en <= not irx_channel_a;`
294			`end if;`
295			`-- channel status enable for the capture register`
296			`if bit_cnt = 26 and ilock = '1' then`
297			`cs_a_en <= irx_channel_a;`
298			`cs_b_en <= not irx_channel_a;`
299			`end if;`
300			`when LONG =>`
301			`short_idx <= '0';`
302			`when others =>`
303			`framerx <= HUNT;`
304			`end case;`
305			`else`
306			`-- there should be 4 pulses in preamble`
307			`if pre_cnt < 7 then`
308			`pre_cnt <= pre_cnt + 1;`
309			`else`
310			`rx_error <= '1';`
311			`framerx <= HUNT;`
312			`end if;`
313			`-- check for correct preamble here`
314			`if pre_cnt = 3 then`
315			`case last_preamble is`
316			`when PRE_X =>`
317			`if new_preamble = PRE_Y then`
318			`framerx <= FRAMESTART;`
319			`irx_channel_a <= '0';`
320			`else`
321			`rx_error <= '1';`
322			`framerx <= HUNT;`
323			`end if;`
324			`when PRE_Y =>`
325			`if new_preamble = PRE_X or new_preamble = PRE_Z then`
326			`irx_channel_a <= '1';`
327			`-- start of new block?`
328			`if new_preamble = PRE_Z then`
329			`rx_block_start <= '1';`
330			`end if;`
331			`framerx <= FRAMESTART;`
332			`else`
333			`rx_error <= '1';`
334			`framerx <= HUNT;`
335			`end if;`
336			`when PRE_Z =>`
337			`if new_preamble = PRE_Y then`
338			`irx_channel_a <= '0';`
339			`framerx <= FRAMESTART;`
340			`else`
341			`rx_error <= '1';`
342			`framerx <= HUNT;`
343			`end if;`
344			`when others =>`
345			`rx_error <= '1';`
346			`framerx <= HUNT;`
347			`end case;`
348			`end if;`
349			`end if;`
350			`else`
351			`rx_data_en <= '0';`
352			`rx_block_start <= '0';`
353			`rx_frame_start <= '0';`
354			`ud_a_en <= '0';`
355			`ud_b_en <= '0';`
356			`cs_a_en <= '0';`
357			`cs_b_en <= '0';`
358			`end if;`
359			`when others =>`
360			`framerx <= IDLE;`
361			`end case;`
362			`end if;`
363			`end process FRX;`
364
365			`end rtl;`

Browse

Tools

Subversion Repositories spdif_interface

[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_phase_det.vhd] - Blame information for rev 20