OpenCores
URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_wb_decoder.vhd] - Blame information for rev 29

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 29 gedra 
----------------------------------------------------------------------
2 
----                                                              ----
3 
---- WISHBONE SPDIF IP Core                                       ----
4 
----                                                              ----
5 
---- This file is part of the SPDIF project                       ----
6 
---- http://www.opencores.org/cores/spdif_interface/              ----
7 
----                                                              ----
8 
---- Description                                                  ----
9 
---- SPDIF receiver: Wishbone bus cycle decoder.                  ----
10 
----                                                              ----
11 
----                                                              ----
12 
---- To Do:                                                       ----
13 
---- -                                                            ----
14 
----                                                              ----
15 
---- Author(s):                                                   ----
16 
---- - Geir Drange, gedra@opencores.org                           ----
17 
----                                                              ----
18 
----------------------------------------------------------------------
19 
----                                                              ----
20 
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
21 
----                                                              ----
22 
---- This source file may be used and distributed without         ----
23 
---- restriction provided that this copyright statement is not    ----
24 
---- removed from the file and that any derivative work contains  ----
25 
---- the original copyright notice and the associated disclaimer. ----
26 
----                                                              ----
27 
---- This source file is free software; you can redistribute it   ----
28 
---- and/or modify it under the terms of the GNU Lesser General   ----
29 
---- Public License as published by the Free Software Foundation; ----
30 
---- either version 2.1 of the License, or (at your option) any   ----
31 
---- later version.                                               ----
32 
----                                                              ----
33 
---- This source is distributed in the hope that it will be       ----
34 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
35 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
36 
---- PURPOSE. See the GNU Lesser General Public License for more  ----
37 
---- details.                                                     ----
38 
----                                                              ----
39 
---- You should have received a copy of the GNU Lesser General    ----
40 
---- Public License along with this source; if not, download it   ----
41 
---- from http://www.opencores.org/lgpl.shtml                     ----
42 
----                                                              ----
43 
----------------------------------------------------------------------
44 
--
45 
-- CVS Revision History
46 
--
47 
-- $Log: not supported by cvs2svn $
48 
--
49 
 
50 
library IEEE;
51 
use IEEE.std_logic_1164.all;
52 
use IEEE.std_logic_arith.all;
53 
--use ieee.std_logic_unsigned.all;
54 
 
55 
entity rx_wb_decoder is
56 
  generic (DATA_WIDTH: integer;
57 
           ADDR_WIDTH: integer);
58 
  port (
59 
    wb_clk_i: in std_logic;             -- wishbone clock
60 
    wb_rst_i: in std_logic;             -- reset signal
61 
    wb_sel_i: in std_logic;             -- select input
62 
    wb_stb_i: in std_logic;             -- strobe input
63 
    wb_we_i: in std_logic;              -- write enable
64 
    wb_cyc_i: in std_logic;             -- cycle input
65 
    wb_bte_i: in std_logic_vector(1 downto 0);  -- burts type extension
66 
    wb_cti_i: in std_logic_vector(2 downto 0);  -- cycle type identifier
67 
    wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0);  -- address
68 
    data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
69 
    wb_ack_o: out std_logic;            -- acknowledge
70 
    wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- data out
71 
    version_rd: out std_logic;          -- Version register read
72 
    config_rd: out std_logic;           -- Config register read
73 
    config_wr: out std_logic;           -- Config register write
74 
    status_rd: out std_logic;           -- Status register read
75 
    intmask_rd: out std_logic;          -- Interrupt mask register read
76 
    intmask_wr: out std_logic;          -- Interrupt mask register write
77 
    intstat_rd: out std_logic;          -- Interrupt status register read
78 
    intstat_wr: out std_logic;          -- Interrupt status register read
79 
    mem_rd: out std_logic;              -- Sample memory read
80 
    mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);  -- memory addr.
81 
    ch_st_cap_rd: out std_logic_vector(7 downto 0);  -- Ch. status cap. read
82 
    ch_st_cap_wr: out std_logic_vector(7 downto 0);  -- Ch. status cap. write
83 
    ch_st_data_rd: out std_logic_vector(7 downto 0));  -- Ch. status data read
84 
end rx_wb_decoder;
85 
 
86 
architecture rtl of rx_wb_decoder is
87 
 
88 
  constant REG_RXVERSION : std_logic_vector(6 downto 0) := "0000000";
89 
  constant REG_RXCONFIG  : std_logic_vector(6 downto 0) := "0000001";
90 
  constant REG_RXSTATUS  : std_logic_vector(6 downto 0) := "0000010";
91 
  constant REG_RXINTMASK : std_logic_vector(6 downto 0) := "0000011";
92 
  constant REG_RXINTSTAT : std_logic_vector(6 downto 0) := "0000100";
93 
  signal iack, iwr, ird : std_logic;
94 
  signal acnt: integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
95 
  signal all_ones : std_logic_vector(ADDR_WIDTH - 1 downto 0);
96 
 
97 
begin
98 
 
99 
  wb_ack_o <= iack;
100 
 
101 
-- acknowledge generation
102 
  ACK: process (wb_clk_i, wb_rst_i)
103 
  begin
104 
    if wb_rst_i = '1' then
105 
      iack <= '0';
106 
    elsif rising_edge(wb_clk_i) then
107 
      if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then
108 
        case wb_cti_i is
109 
          when "010" => -- incrementing burst
110 
            case wb_bte_i is -- burst extension
111 
              when "00" => -- linear burst
112 
                iack <= '1';
113 
              when others => -- all other treated assert classic cycle
114 
                iack <= not iack;
115 
            end case;
116 
          when "111" => -- end of burst
117 
            iack <= not iack;
118 
          when others => -- all other treated assert classic cycle
119 
            iack <= not iack;
120 
        end case;
121 
      else
122 
        iack <= '0';
123 
      end if;
124 
    end if;
125 
  end process ACK;
126 
 
127 
-- write generation
128 
  WR: process (wb_clk_i, wb_rst_i)
129 
  begin
130 
    if wb_rst_i = '1' then
131 
      iwr <= '0';
132 
    elsif rising_edge(wb_clk_i) then
133 
      if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
134 
        wb_we_i = '1' then
135 
        case wb_cti_i is
136 
          when "010" => -- incrementing burst
137 
            case wb_bte_i is -- burst extension
138 
              when "00" => -- linear burst
139 
                iwr <= '1';
140 
              when others => -- all other treated assert classic cycle
141 
                iwr <= not iwr;
142 
            end case;
143 
          when "111" => -- end of burst
144 
            iwr <= not iwr;
145 
          when others => -- all other treated assert classic cycle
146 
            iwr <= not iwr;
147 
        end case;
148 
      else
149 
        iwr <= '0';
150 
      end if;
151 
    end if;
152 
  end process WR;
153 
 
154 
-- read generation
155 
  ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
156 
         wb_we_i = '0' else '0';
157 
 
158 
-- sample memory read address. This needs special attention due to read latency
159 
  mem_addr <= CONV_STD_LOGIC_VECTOR(acnt, ADDR_WIDTH - 1) when
160 
              wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
161 
              wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
162 
 
163 
  all_ones <= (others => '1');
164 
 
165 
  SMA: process (wb_clk_i, wb_rst_i)
166 
  begin
167 
    if wb_rst_i = '1' then
168 
      acnt <= 0;
169 
    elsif rising_edge(wb_clk_i) then
170 
      if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then
171 
        if iack = '0' then
172 
          if wb_adr_i = all_ones then
173 
            acnt <= 0;
174 
          else
175 
            acnt <= CONV_INTEGER(wb_adr_i) + 1;
176 
          end if;
177 
        else
178 
          if acnt < 2**(ADDR_WIDTH - 1) - 1 then
179 
            acnt <= acnt + 1;
180 
          else
181 
            acnt <= 0;
182 
          end if;
183 
        end if;
184 
      end if;
185 
    end if;
186 
  end process SMA;
187 
 
188 
-- read and write strobe generation
189 
 
190 
  version_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXVERSION and ird = '1'
191 
                else '0';
192 
  config_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and ird = '1'
193 
               else '0';
194 
  config_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and iwr = '1'
195 
               else '0';
196 
  status_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXSTATUS and ird = '1'
197 
               else '0';
198 
  intmask_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and ird = '1'
199 
                else '0';
200 
  intmask_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and iwr = '1'
201 
                else '0';
202 
  intstat_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and ird = '1'
203 
                else '0';
204 
  intstat_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and iwr = '1'
205 
                else '0';
206 
  mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
207 
 
208 
-- capture register strobes
209 
  CR32: if DATA_WIDTH = 32 generate
210 
    CRST: for k in 0 to 7 generate
211 
      ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
212 
                         and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k,4)
213 
                         else '0';
214 
      ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
215 
                         and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k,4)
216 
                         else '0';
217 
      ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
218 
                          and wb_adr_i(3 downto 0) = CONV_STD_LOGIC_VECTOR(2*k+1,4)
219 
                          else '0';
220 
    end generate CRST;
221 
  end generate CR32;
222 
  CR16: if DATA_WIDTH = 16 generate
223 
    ch_st_cap_rd(7 downto 0) <= (others => '0');
224 
    ch_st_cap_wr(7 downto 0) <= (others => '0');
225 
    ch_st_data_rd(7 downto 0) <= (others => '0');
226 
  end generate CR16;
227 
 
228 
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.