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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [rx_wb_decoder.vhd] - Blame information for rev 73

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1 29 gedra 
----------------------------------------------------------------------
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----                                                              ----
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---- WISHBONE SPDIF IP Core                                       ----
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----                                                              ----
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---- This file is part of the SPDIF project                       ----
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---- http://www.opencores.org/cores/spdif_interface/              ----
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----                                                              ----
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---- Description                                                  ----
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---- SPDIF receiver: Wishbone bus cycle decoder.                  ----
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----                                                              ----
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----                                                              ----
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---- To Do:                                                       ----
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---- -                                                            ----
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----                                                              ----
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---- Author(s):                                                   ----
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---- - Geir Drange, gedra@opencores.org                           ----
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----                                                              ----
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----------------------------------------------------------------------
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----                                                              ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
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----                                                              ----
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---- This source file may be used and distributed without         ----
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---- restriction provided that this copyright statement is not    ----
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---- removed from the file and that any derivative work contains  ----
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---- the original copyright notice and the associated disclaimer. ----
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----                                                              ----
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---- This source file is free software; you can redistribute it   ----
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---- and/or modify it under the terms of the GNU Lesser General   ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any   ----
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---- later version.                                               ----
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----                                                              ----
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---- This source is distributed in the hope that it will be       ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
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---- PURPOSE. See the GNU Lesser General Public License for more  ----
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---- details.                                                     ----
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----                                                              ----
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---- You should have received a copy of the GNU Lesser General    ----
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---- Public License along with this source; if not, download it   ----
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---- from http://www.opencores.org/lgpl.shtml                     ----
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----                                                              ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
48 72 gedra 
-- Revision 1.4  2005/03/27 14:05:22  gedra
49 
-- Fix: Include MSB of address bus in register strobe generation
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--
51 70 gedra 
-- Revision 1.3  2004/06/26 14:14:47  gedra
52 
-- Converted to numeric_std and fixed a few bugs.
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--
54 37 gedra 
-- Revision 1.2  2004/06/24 19:25:03  gedra
55 
-- Added data output.
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--
57 31 gedra 
-- Revision 1.1  2004/06/23 18:09:57  gedra
58 
-- Wishbone bus cycle decoder.
59 29 gedra 
--
60 31 gedra 
--
61 29 gedra 
 
62 37 gedra 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
65 29 gedra 
 
66 72 gedra 
entity rx_wb_decoder is
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   generic (DATA_WIDTH : integer;
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            ADDR_WIDTH : integer);
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   port (
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      wb_clk_i      : in  std_logic;    -- wishbone clock
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      wb_rst_i      : in  std_logic;    -- reset signal
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      wb_sel_i      : in  std_logic;    -- select input
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      wb_stb_i      : in  std_logic;    -- strobe input
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      wb_we_i       : in  std_logic;    -- write enable
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      wb_cyc_i      : in  std_logic;    -- cycle input
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      wb_bte_i      : in  std_logic_vector(1 downto 0);  -- burts type extension
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      wb_cti_i      : in  std_logic_vector(2 downto 0);  -- cycle type identifier
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      wb_adr_i      : in  std_logic_vector(ADDR_WIDTH - 1 downto 0);  -- address
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      data_out      : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- internal bus
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      wb_ack_o      : out std_logic;    -- acknowledge
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      wb_dat_o      : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- data out
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      version_rd    : out std_logic;    -- Version register read
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      config_rd     : out std_logic;    -- Config register read
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      config_wr     : out std_logic;    -- Config register write
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      status_rd     : out std_logic;    -- Status register read
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      intmask_rd    : out std_logic;    -- Interrupt mask register read
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      intmask_wr    : out std_logic;    -- Interrupt mask register write
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      intstat_rd    : out std_logic;    -- Interrupt status register read
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      intstat_wr    : out std_logic;    -- Interrupt status register read
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      mem_rd        : out std_logic;    -- Sample memory read
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      mem_addr      : out std_logic_vector(ADDR_WIDTH - 2 downto 0);  -- memory addr.
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      ch_st_cap_rd  : out std_logic_vector(7 downto 0);  -- Ch. status cap. read
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      ch_st_cap_wr  : out std_logic_vector(7 downto 0);  -- Ch. status cap. write
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      ch_st_data_rd : out std_logic_vector(7 downto 0));  -- Ch. status data read
95 29 gedra 
end rx_wb_decoder;
96 
 
97 
architecture rtl of rx_wb_decoder is
98 72 gedra 
 
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   constant REG_RXVERSION : std_logic_vector(6 downto 0) := "0000000";
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   constant REG_RXCONFIG  : std_logic_vector(6 downto 0) := "0000001";
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   constant REG_RXSTATUS  : std_logic_vector(6 downto 0) := "0000010";
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   constant REG_RXINTMASK : std_logic_vector(6 downto 0) := "0000011";
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   constant REG_RXINTSTAT : std_logic_vector(6 downto 0) := "0000100";
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   signal iack, iwr, ird  : std_logic;
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   signal acnt            : integer range 0 to 2**(ADDR_WIDTH - 1) - 1;
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   signal all_ones        : std_logic_vector(ADDR_WIDTH - 1 downto 0);
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   signal rdout           : std_logic_vector(DATA_WIDTH - 1 downto 0);
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109 
begin
110 29 gedra 
 
111 72 gedra 
   wb_ack_o <= iack;
112 29 gedra 
 
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-- acknowledge generation
114 72 gedra 
   ACK : process (wb_clk_i, wb_rst_i)
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   begin
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      if wb_rst_i = '1' then
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         iack <= '0';
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      elsif rising_edge(wb_clk_i) then
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         if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' then
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            case wb_cti_i is
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               when "010" =>            -- incrementing burst
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                  case wb_bte_i is      -- burst extension
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                     when "00" =>       -- linear burst
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                        iack <= '1';
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                     when others =>  -- all other treated assert classic cycle
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                        iack <= not iack;
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                  end case;
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               when "111" =>            -- end of burst
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                  iack <= not iack;
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               when others =>        -- all other treated assert classic cycle
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                  iack <= not iack;
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            end case;
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         else
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            iack <= '0';
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         end if;
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      end if;
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   end process ACK;
138 29 gedra 
 
139 
-- write generation
140 72 gedra 
   WR : process (wb_clk_i, wb_rst_i)
141 
   begin
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      if wb_rst_i = '1' then
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         iwr <= '0';
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      elsif rising_edge(wb_clk_i) then
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         if wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
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            wb_we_i = '1' then
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            case wb_cti_i is
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               when "010" =>            -- incrementing burst
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                  case wb_bte_i is      -- burst extension
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                     when "00" =>       -- linear burst
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                        iwr <= '1';
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                     when others =>  -- all other treated assert classic cycle
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                        iwr <= not iwr;
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                  end case;
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               when "111" =>            -- end of burst
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                  iwr <= not iwr;
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               when others =>  -- all other treated assert classic cycle
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                  iwr <= not iwr;
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            end case;
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         else
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            iwr <= '0';
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         end if;
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      end if;
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   end process WR;
165 29 gedra 
 
166 
-- read generation
167 72 gedra 
   ird <= '1' when wb_cyc_i = '1' and wb_sel_i = '1' and wb_stb_i = '1' and
168 
          wb_we_i = '0' else '0';
169 29 gedra 
 
170 72 gedra 
   wb_dat_o <= data_out when wb_adr_i(ADDR_WIDTH - 1) = '1' else rdout;
171 31 gedra 
 
172 72 gedra 
   DREG : process (wb_clk_i)            -- clock data from registers
173 
   begin
174 
      if rising_edge(wb_clk_i) then
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         rdout <= data_out;
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      end if;
177 
   end process DREG;
178 
 
179 29 gedra 
-- sample memory read address. This needs special attention due to read latency
180 72 gedra 
   mem_addr <= std_logic_vector(to_unsigned(acnt, ADDR_WIDTH - 1)) when
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               wb_cti_i = "010" and wb_we_i = '0' and iack = '1' and
182 
               wb_bte_i = "00" else wb_adr_i(ADDR_WIDTH - 2 downto 0);
183 
 
184 
   all_ones(ADDR_WIDTH - 1 downto 0) <= (others => '1');
185 
 
186 
   SMA : process (wb_clk_i, wb_rst_i)
187 
   begin
188 
      if wb_rst_i = '1' then
189 
         acnt <= 0;
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      elsif rising_edge(wb_clk_i) then
191 
         if wb_cti_i = "010" and wb_we_i = '0' and wb_bte_i = "00" then
192 
            if iack = '0' then
193 
               if wb_adr_i = all_ones then
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                  acnt <= 0;
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               else
196 
                  acnt <= to_integer(unsigned(wb_adr_i)) + 1;
197 
               end if;
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            else
199 
               if acnt < 2**(ADDR_WIDTH - 1) - 1 then
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                  acnt <= acnt + 1;
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               else
202 
                  acnt <= 0;
203 
               end if;
204 
            end if;
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         end if;
206 29 gedra 
      end if;
207 72 gedra 
   end process SMA;
208 
 
209 29 gedra 
-- read and write strobe generation
210 72 gedra 
 
211 
   version_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXVERSION and ird = '1'
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                 and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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   config_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and ird = '1'
214 70 gedra 
                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
215 72 gedra 
   config_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXCONFIG and iwr = '1'
216 70 gedra 
                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
217 72 gedra 
   status_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXSTATUS and ird = '1'
218 70 gedra 
                and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
219 72 gedra 
   intmask_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and ird = '1'
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                 and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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   intmask_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTMASK and iwr = '1'
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                 and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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   intstat_rd <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and ird = '1'
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                 and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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   intstat_wr <= '1' when wb_adr_i(6 downto 0) = REG_RXINTSTAT and iwr = '1'
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                 and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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   mem_rd <= '1' when wb_adr_i(ADDR_WIDTH - 1) = '1' and ird = '1' else '0';
228 29 gedra 
 
229 
-- capture register strobes
230 72 gedra 
   CR32 : if DATA_WIDTH = 32 generate
231 
      CRST : for k in 0 to 7 generate
232 
         ch_st_cap_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
233 
                            and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k, 4))
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                            and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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         ch_st_cap_wr(k) <= '1' when iwr = '1' and wb_adr_i(6 downto 4) = "001"
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                            and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k, 4))
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                            and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
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         ch_st_data_rd(k) <= '1' when ird = '1' and wb_adr_i(6 downto 4) = "001"
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                             and wb_adr_i(3 downto 0) = std_logic_vector(to_unsigned(2*k+1, 4))
240 
                             and wb_adr_i(ADDR_WIDTH - 1) = '0' else '0';
241 
      end generate CRST;
242 
   end generate CR32;
243 
   CR16 : if DATA_WIDTH = 16 generate
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      ch_st_cap_rd(7 downto 0)  <= (others => '0');
245 
      ch_st_cap_wr(7 downto 0)  <= (others => '0');
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      ch_st_data_rd(7 downto 0) <= (others => '0');
247 
   end generate CR16;
248 
 
249 29 gedra 
end rtl;

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