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gedra |
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---- ----
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---- WISHBONE SPDIF IP Core ----
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---- ----
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---- This file is part of the SPDIF project ----
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---- http://www.opencores.org/cores/spdif_interface/ ----
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---- ----
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---- Description ----
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---- Bit buffer holding 2x192 bits of either channel status or ----
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---- user data for the transmitter. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Geir Drange, gedra@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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gedra |
-- Revision 1.3 2004/07/19 16:59:43 gedra
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-- Fixed bug.
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--
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gedra |
-- Revision 1.2 2004/07/17 17:21:11 gedra
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-- Fixed bug.
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--
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gedra |
-- Revision 1.1 2004/07/14 17:58:19 gedra
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-- Transmitter channel status buffer.
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gedra |
--
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--
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gedra |
--
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gedra |
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library ieee;
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gedra |
use ieee.std_logic_1164.all;
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gedra |
use ieee.numeric_std.all;
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gedra |
entity tx_bitbuf is
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generic (ENABLE_BUFFER : integer range 0 to 1);
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port (
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wb_clk_i : in std_logic; -- clock
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wb_rst_i : in std_logic; -- reset
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buf_wr : in std_logic; -- buffer write strobe
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wb_adr_i : in std_logic_vector(4 downto 0); -- address
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wb_dat_i : in std_logic_vector(15 downto 0); -- data
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buf_data_a : out std_logic_vector(191 downto 0);
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buf_data_b : out std_logic_vector(191 downto 0));
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gedra |
end tx_bitbuf;
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architecture rtl of tx_bitbuf is
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type buf_type is array (0 to 23) of std_logic_vector(7 downto 0);
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signal buffer_a, buffer_b : buf_type;
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gedra |
begin
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gedra |
-- the byte buffer is 192 bits (24 bytes) for each channel
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EB : if ENABLE_BUFFER = 1 generate
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WBUF : process (wb_clk_i, wb_rst_i)
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begin
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if wb_rst_i = '1' then
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for i in 0 to 23 loop
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buffer_a(i) <= (others => '0');
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buffer_b(i) <= (others => '0');
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end loop;
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elsif rising_edge(wb_clk_i) then
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if buf_wr = '1' and to_integer(unsigned(wb_adr_i)) < 24 then
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buffer_a(to_integer(unsigned(wb_adr_i))) <= wb_dat_i(7 downto 0);
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buffer_b(to_integer(unsigned(wb_adr_i))) <= wb_dat_i(15 downto 8);
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end if;
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end if;
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end process WBUF;
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VGEN : for k in 0 to 23 generate
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buf_data_a(8 * k + 7 downto 8 * k) <= buffer_a(k);
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buf_data_b(8 * k + 7 downto 8 * k) <= buffer_b(k);
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end generate VGEN;
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end generate EB;
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-- if the byte buffer is not enabled, set all bits to zero
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NEB : if ENABLE_BUFFER = 0 generate
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buf_data_a(191 downto 0) <= (others => '0');
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buf_data_b(191 downto 0) <= (others => '0');
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end generate NEB;
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gedra |
end rtl;
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