| 1 |
47 |
gedra |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- WISHBONE SPDIF IP Core ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the SPDIF project ----
|
| 6 |
|
|
---- http://www.opencores.org/cores/spdif_interface/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description ----
|
| 9 |
|
|
---- Bit buffer holding 2x192 bits of either channel status or ----
|
| 10 |
|
|
---- user data for the transmitter. ----
|
| 11 |
|
|
---- ----
|
| 12 |
|
|
---- To Do: ----
|
| 13 |
|
|
---- - ----
|
| 14 |
|
|
---- ----
|
| 15 |
|
|
---- Author(s): ----
|
| 16 |
|
|
---- - Geir Drange, gedra@opencores.org ----
|
| 17 |
|
|
---- ----
|
| 18 |
|
|
----------------------------------------------------------------------
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
|
| 21 |
|
|
---- ----
|
| 22 |
|
|
---- This source file may be used and distributed without ----
|
| 23 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 24 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 25 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 26 |
|
|
---- ----
|
| 27 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 28 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 29 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 30 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 31 |
|
|
---- later version. ----
|
| 32 |
|
|
---- ----
|
| 33 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 34 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 35 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 36 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 37 |
|
|
---- details. ----
|
| 38 |
|
|
---- ----
|
| 39 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 40 |
|
|
---- Public License along with this source; if not, download it ----
|
| 41 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 42 |
|
|
---- ----
|
| 43 |
|
|
----------------------------------------------------------------------
|
| 44 |
|
|
--
|
| 45 |
|
|
-- CVS Revision History
|
| 46 |
|
|
--
|
| 47 |
|
|
-- $Log: not supported by cvs2svn $
|
| 48 |
|
|
--
|
| 49 |
|
|
--
|
| 50 |
|
|
|
| 51 |
|
|
library ieee;
|
| 52 |
|
|
use ieee.std_logic_1164.all;
|
| 53 |
|
|
use ieee.numeric_std.all;
|
| 54 |
|
|
|
| 55 |
|
|
entity tx_bitbuf is
|
| 56 |
|
|
generic (ENABLE_BUFFER: integer range 0 to 1);
|
| 57 |
|
|
port (
|
| 58 |
|
|
wb_clk_i: in std_logic; -- clock
|
| 59 |
|
|
wb_rst_i: in std_logic; -- reset
|
| 60 |
|
|
buf_wr: in std_logic; -- buffer write strobe
|
| 61 |
|
|
wb_adr_i: in std_logic_vector(4 downto 0); -- address
|
| 62 |
|
|
wb_dat_i: in std_logic_vector(15 downto 0); -- data
|
| 63 |
|
|
buf_data_a: out std_logic_vector(191 downto 0);
|
| 64 |
|
|
buf_data_b: out std_logic_vector(191 downto 0));
|
| 65 |
|
|
end tx_bitbuf;
|
| 66 |
|
|
|
| 67 |
|
|
architecture rtl of tx_bitbuf is
|
| 68 |
|
|
|
| 69 |
|
|
begin
|
| 70 |
|
|
|
| 71 |
|
|
-- the byte buffer is 192 bits (24 bytes) for each channel
|
| 72 |
|
|
EB: if ENABLE_BUFFER = 1 generate
|
| 73 |
|
|
WBUF: process (wb_clk_i, wb_rst_i)
|
| 74 |
|
|
begin
|
| 75 |
|
|
if wb_rst_i = '1' then
|
| 76 |
|
|
buf_data_a(191 downto 0) <= (others => '0');
|
| 77 |
|
|
buf_data_b(191 downto 0) <= (others => '0');
|
| 78 |
|
|
elsif rising_edge(wb_clk_i) then
|
| 79 |
|
|
if buf_wr = '1' then
|
| 80 |
|
|
buf_data_a(8*to_integer(unsigned(wb_adr_i)) + 7 downto
|
| 81 |
|
|
8*to_integer(unsigned(wb_adr_i))) <= wb_dat_i(7 downto 0);
|
| 82 |
|
|
buf_data_b(8*to_integer(unsigned(wb_adr_i)) + 7 downto
|
| 83 |
|
|
8*to_integer(unsigned(wb_adr_i))) <= wb_dat_i(15 downto 8);
|
| 84 |
|
|
end if;
|
| 85 |
|
|
end if;
|
| 86 |
|
|
end process WBUF;
|
| 87 |
|
|
end generate EB;
|
| 88 |
|
|
|
| 89 |
|
|
-- if the byte buffer is not enabled, set all bits to zero
|
| 90 |
|
|
NEB: if ENABLE_BUFFER = 0 generate
|
| 91 |
|
|
buf_data_a(191 downto 0) <= (others => '0');
|
| 92 |
|
|
buf_data_b(191 downto 0) <= (others => '0');
|
| 93 |
|
|
end generate NEB;
|
| 94 |
|
|
|
| 95 |
|
|
end rtl;
|
