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----------------------------------------------------------------------
----                                                              ----
---- WISHBONE SPDIF IP Core                                       ----
----                                                              ----
---- This file is part of the SPDIF project                       ----
---- http://www.opencores.org/cores/spdif_interface/              ----
----                                                              ----
---- Description                                                  ----
---- SPDIF transmitter component package.                         ----
----                                                              ----
----                                                              ----
---- To Do:                                                       ----
---- -                                                            ----
----                                                              ----
---- Author(s):                                                   ----
---- - Geir Drange, gedra@opencores.org                           ----
----                                                              ----
----------------------------------------------------------------------
----                                                              ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG                 ----
----                                                              ----
---- This source file may be used and distributed without         ----
---- restriction provided that this copyright statement is not    ----
---- removed from the file and that any derivative work contains  ----
---- the original copyright notice and the associated disclaimer. ----
----                                                              ----
---- This source file is free software; you can redistribute it   ----
---- and/or modify it under the terms of the GNU Lesser General   ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any   ----
---- later version.                                               ----
----                                                              ----
---- This source is distributed in the hope that it will be       ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
---- PURPOSE. See the GNU Lesser General Public License for more  ----
---- details.                                                     ----
----                                                              ----
---- You should have received a copy of the GNU Lesser General    ----
---- Public License along with this source; if not, download it   ----
---- from http://www.opencores.org/lgpl.shtml                     ----
----                                                              ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3  2004/07/19 16:59:31  gedra
-- Added component.
--
-- Revision 1.2  2004/07/14 17:58:49  gedra
-- Added new components.
--
-- Revision 1.1  2004/07/13 18:30:25  gedra
-- Transmitter component declarations.
--
-- 
--
 
library ieee;
use ieee.std_logic_1164.all;
 
package tx_package is
 
-- components used in the transmitter
 
   component gen_control_reg
      generic (DATA_WIDTH      : integer;
               -- note that this vector is (0 to xx), reverse order
               ACTIVE_BIT_MASK : std_logic_vector);
      port (
         clk       : in  std_logic;     -- clock  
         rst       : in  std_logic;     -- reset
         ctrl_wr   : in  std_logic;     -- control register write       
         ctrl_rd   : in  std_logic;     -- control register read
         ctrl_din  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
         ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);
         ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));
   end component;
 
   component gen_event_reg
      generic (DATA_WIDTH : integer);
      port (
         clk      : in  std_logic;      -- clock  
         rst      : in  std_logic;      -- reset
         evt_wr   : in  std_logic;      -- event register write  
         evt_rd   : in  std_logic;      -- event register read
         evt_din  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- write data
         event    : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- event vector
         evt_mask : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- irq mask
         evt_en   : in  std_logic;      -- irq enable
         evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- read data
         evt_irq  : out std_logic);     -- interrupt  request
   end component;
 
   component dpram
      generic (DATA_WIDTH : positive;
               RAM_WIDTH  : positive);
      port (
         clk     : in  std_logic;
         rst     : in  std_logic;       -- reset is optional, not used here
         din     : in  std_logic_vector(DATA_WIDTH - 1 downto 0);
         wr_en   : in  std_logic;
         rd_en   : in  std_logic;
         wr_addr : in  std_logic_vector(RAM_WIDTH - 1 downto 0);
         rd_addr : in  std_logic_vector(RAM_WIDTH - 1 downto 0);
         dout    : out std_logic_vector(DATA_WIDTH - 1 downto 0));
   end component;
 
   component tx_wb_decoder
      generic (DATA_WIDTH : integer;
               ADDR_WIDTH : integer);
      port (
         wb_clk_i     : in  std_logic;  -- wishbone clock
         wb_rst_i     : in  std_logic;  -- reset signal
         wb_sel_i     : in  std_logic;  -- select input
         wb_stb_i     : in  std_logic;  -- strobe input
         wb_we_i      : in  std_logic;  -- write enable
         wb_cyc_i     : in  std_logic;  -- cycle input
         wb_bte_i     : in  std_logic_vector(1 downto 0);  -- burts type extension
         wb_cti_i     : in  std_logic_vector(2 downto 0);  -- cycle type identifier
         wb_adr_i     : in  std_logic_vector(ADDR_WIDTH - 1 downto 0);  -- address
         data_out     : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- internal bus
         wb_ack_o     : out std_logic;  -- acknowledge
         wb_dat_o     : out std_logic_vector(DATA_WIDTH - 1 downto 0);  -- data out
         version_rd   : out std_logic;  -- Version register read 
         config_rd    : out std_logic;  -- Config register read
         config_wr    : out std_logic;  -- Config register write
         chstat_rd    : out std_logic;  -- Channel Status register read
         chstat_wr    : out std_logic;  -- Channel Status register write
         intmask_rd   : out std_logic;  -- Interrupt mask register read
         intmask_wr   : out std_logic;  -- Interrupt mask register write
         intstat_rd   : out std_logic;  -- Interrupt status register read
         intstat_wr   : out std_logic;  -- Interrupt status register read
         mem_wr       : out std_logic;  -- Sample memory write
         user_data_wr : out std_logic;  -- User data write
         ch_status_wr : out std_logic);                    -- Ch. status write
   end component;
 
   component tx_ver_reg
      generic (DATA_WIDTH    : integer;
               ADDR_WIDTH    : integer;
               USER_DATA_BUF : integer;
               CH_STAT_BUF   : integer);
      port (
         ver_rd   : in  std_logic;      -- version register read
         ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));
   end component;
 
   component tx_bitbuf
      generic (ENABLE_BUFFER : integer range 0 to 1);
      port (
         wb_clk_i   : in  std_logic;    -- clock
         wb_rst_i   : in  std_logic;    -- reset
         buf_wr     : in  std_logic;    -- buffer write strobe
         wb_adr_i   : in  std_logic_vector(4 downto 0);   -- address
         wb_dat_i   : in  std_logic_vector(15 downto 0);  -- data
         buf_data_a : out std_logic_vector(191 downto 0);
         buf_data_b : out std_logic_vector(191 downto 0));
   end component;
 
   component tx_encoder
      generic (DATA_WIDTH : integer range 16 to 32;
               ADDR_WIDTH : integer range 8 to 64);
      port (
         wb_clk_i     : in  std_logic;  -- clock
         conf_mode    : in  std_logic_vector(3 downto 0);  -- sample format
         conf_ratio   : in  std_logic_vector(7 downto 0);  -- clock divider
         conf_udaten  : in  std_logic_vector(1 downto 0);  -- user data control
         conf_chsten  : in  std_logic_vector(1 downto 0);  -- ch. status control
         conf_txdata  : in  std_logic;  -- sample data enable
         conf_txen    : in  std_logic;  -- spdif signal enable
         user_data_a  : in  std_logic_vector(191 downto 0);  -- ch. a user data
         user_data_b  : in  std_logic_vector(191 downto 0);  -- ch. b user data
         ch_stat_a    : in  std_logic_vector(191 downto 0);  -- ch. a status
         ch_stat_b    : in  std_logic_vector(191 downto 0);  -- ch. b status
         chstat_freq  : in  std_logic_vector(1 downto 0);  -- sample freq.
         chstat_gstat : in  std_logic;  -- generation status
         chstat_preem : in  std_logic;  -- preemphasis status
         chstat_copy  : in  std_logic;  -- copyright bit
         chstat_audio : in  std_logic;  -- data format
         sample_data  : in  std_logic_vector(DATA_WIDTH - 1 downto 0);  -- audio data
         mem_rd       : out std_logic;  -- sample buffer read
         sample_addr  : out std_logic_vector(ADDR_WIDTH - 2 downto 0);  -- address
         evt_lcsbf    : out std_logic;  -- lower ch.st./user data buf empty 
         evt_hcsbf    : out std_logic;  -- higher ch.st/user data buf empty 
         evt_hsbf     : out std_logic;  -- higher sample buf empty event
         evt_lsbf     : out std_logic;  -- lower sample buf empty event
         spdif_tx_o   : out std_logic);
   end component;
 
end tx_package;

Line No.	Rev	Author	Line
1	45	gedra	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- WISHBONE SPDIF IP Core ----`
4			`---- ----`
5			`---- This file is part of the SPDIF project ----`
6			`---- http://www.opencores.org/cores/spdif_interface/ ----`
7			`---- ----`
8			`---- Description ----`
9			`---- SPDIF transmitter component package. ----`
10			`---- ----`
11			`---- ----`
12			`---- To Do: ----`
13			`---- - ----`
14			`---- ----`
15			`---- Author(s): ----`
16			`---- - Geir Drange, gedra@opencores.org ----`
17			`---- ----`
18			`----------------------------------------------------------------------`
19			`---- ----`
20			`---- Copyright (C) 2004 Authors and OPENCORES.ORG ----`
21			`---- ----`
22			`---- This source file may be used and distributed without ----`
23			`---- restriction provided that this copyright statement is not ----`
24			`---- removed from the file and that any derivative work contains ----`
25			`---- the original copyright notice and the associated disclaimer. ----`
26			`---- ----`
27			`---- This source file is free software; you can redistribute it ----`
28			`---- and/or modify it under the terms of the GNU Lesser General ----`
29			`---- Public License as published by the Free Software Foundation; ----`
30			`---- either version 2.1 of the License, or (at your option) any ----`
31			`---- later version. ----`
32			`---- ----`
33			`---- This source is distributed in the hope that it will be ----`
34			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
35			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
36			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
37			`---- details. ----`
38			`---- ----`
39			`---- You should have received a copy of the GNU Lesser General ----`
40			`---- Public License along with this source; if not, download it ----`
41			`---- from http://www.opencores.org/lgpl.shtml ----`
42			`---- ----`
43			`----------------------------------------------------------------------`
44			`--`
45			`-- CVS Revision History`
46			`--`
47			`-- $Log: not supported by cvs2svn $`
48	72	gedra	`-- Revision 1.3 2004/07/19 16:59:31 gedra`
49			`-- Added component.`
50			`--`
51	57	gedra	`-- Revision 1.2 2004/07/14 17:58:49 gedra`
52			`-- Added new components.`
53			`--`
54	48	gedra	`-- Revision 1.1 2004/07/13 18:30:25 gedra`
55			`-- Transmitter component declarations.`
56			`--`
57	45	gedra	`--`
58			`--`
59	72	gedra
60	45	gedra	`library ieee;`
61	72	gedra	`use ieee.std_logic_1164.all;`
62	45	gedra
63			`package tx_package is`
64
65	48	gedra	`-- components used in the transmitter`
66	72	gedra
67			`component gen_control_reg`
68			`generic (DATA_WIDTH : integer;`
69			`-- note that this vector is (0 to xx), reverse order`
70			`ACTIVE_BIT_MASK : std_logic_vector);`
71			`port (`
72			`clk : in std_logic; -- clock`
73			`rst : in std_logic; -- reset`
74			`ctrl_wr : in std_logic; -- control register write`
75			`ctrl_rd : in std_logic; -- control register read`
76			`ctrl_din : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
77			`ctrl_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0);`
78			`ctrl_bits : out std_logic_vector(DATA_WIDTH - 1 downto 0));`
79			`end component;`
80	45	gedra
81	72	gedra	`component gen_event_reg`
82			`generic (DATA_WIDTH : integer);`
83			`port (`
84			`clk : in std_logic; -- clock`
85			`rst : in std_logic; -- reset`
86			`evt_wr : in std_logic; -- event register write`
87			`evt_rd : in std_logic; -- event register read`
88			`evt_din : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data`
89			`event : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector`
90			`evt_mask : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask`
91			`evt_en : in std_logic; -- irq enable`
92			`evt_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data`
93			`evt_irq : out std_logic); -- interrupt request`
94			`end component;`
95	45	gedra
96	72	gedra	`component dpram`
97			`generic (DATA_WIDTH : positive;`
98			`RAM_WIDTH : positive);`
99			`port (`
100			`clk : in std_logic;`
101			`rst : in std_logic; -- reset is optional, not used here`
102			`din : in std_logic_vector(DATA_WIDTH - 1 downto 0);`
103			`wr_en : in std_logic;`
104			`rd_en : in std_logic;`
105			`wr_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);`
106			`rd_addr : in std_logic_vector(RAM_WIDTH - 1 downto 0);`
107			`dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));`
108			`end component;`
109	45	gedra
110	72	gedra	`component tx_wb_decoder`
111			`generic (DATA_WIDTH : integer;`
112			`ADDR_WIDTH : integer);`
113			`port (`
114			`wb_clk_i : in std_logic; -- wishbone clock`
115			`wb_rst_i : in std_logic; -- reset signal`
116			`wb_sel_i : in std_logic; -- select input`
117			`wb_stb_i : in std_logic; -- strobe input`
118			`wb_we_i : in std_logic; -- write enable`
119			`wb_cyc_i : in std_logic; -- cycle input`
120			`wb_bte_i : in std_logic_vector(1 downto 0); -- burts type extension`
121			`wb_cti_i : in std_logic_vector(2 downto 0); -- cycle type identifier`
122			`wb_adr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address`
123			`data_out : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus`
124			`wb_ack_o : out std_logic; -- acknowledge`
125			`wb_dat_o : out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out`
126			`version_rd : out std_logic; -- Version register read`
127			`config_rd : out std_logic; -- Config register read`
128			`config_wr : out std_logic; -- Config register write`
129			`chstat_rd : out std_logic; -- Channel Status register read`
130			`chstat_wr : out std_logic; -- Channel Status register write`
131			`intmask_rd : out std_logic; -- Interrupt mask register read`
132			`intmask_wr : out std_logic; -- Interrupt mask register write`
133			`intstat_rd : out std_logic; -- Interrupt status register read`
134			`intstat_wr : out std_logic; -- Interrupt status register read`
135			`mem_wr : out std_logic; -- Sample memory write`
136			`user_data_wr : out std_logic; -- User data write`
137			`ch_status_wr : out std_logic); -- Ch. status write`
138			`end component;`
139	48	gedra
140	72	gedra	`component tx_ver_reg`
141			`generic (DATA_WIDTH : integer;`
142			`ADDR_WIDTH : integer;`
143			`USER_DATA_BUF : integer;`
144			`CH_STAT_BUF : integer);`
145			`port (`
146			`ver_rd : in std_logic; -- version register read`
147			`ver_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0));`
148			`end component;`
149	48	gedra
150	72	gedra	`component tx_bitbuf`
151			`generic (ENABLE_BUFFER : integer range 0 to 1);`
152			`port (`
153			`wb_clk_i : in std_logic; -- clock`
154			`wb_rst_i : in std_logic; -- reset`
155			`buf_wr : in std_logic; -- buffer write strobe`
156			`wb_adr_i : in std_logic_vector(4 downto 0); -- address`
157			`wb_dat_i : in std_logic_vector(15 downto 0); -- data`
158			`buf_data_a : out std_logic_vector(191 downto 0);`
159			`buf_data_b : out std_logic_vector(191 downto 0));`
160			`end component;`
161	57	gedra
162	72	gedra	`component tx_encoder`
163			`generic (DATA_WIDTH : integer range 16 to 32;`
164			`ADDR_WIDTH : integer range 8 to 64);`
165			`port (`
166			`wb_clk_i : in std_logic; -- clock`
167			`conf_mode : in std_logic_vector(3 downto 0); -- sample format`
168			`conf_ratio : in std_logic_vector(7 downto 0); -- clock divider`
169			`conf_udaten : in std_logic_vector(1 downto 0); -- user data control`
170			`conf_chsten : in std_logic_vector(1 downto 0); -- ch. status control`
171			`conf_txdata : in std_logic; -- sample data enable`
172			`conf_txen : in std_logic; -- spdif signal enable`
173			`user_data_a : in std_logic_vector(191 downto 0); -- ch. a user data`
174			`user_data_b : in std_logic_vector(191 downto 0); -- ch. b user data`
175			`ch_stat_a : in std_logic_vector(191 downto 0); -- ch. a status`
176			`ch_stat_b : in std_logic_vector(191 downto 0); -- ch. b status`
177			`chstat_freq : in std_logic_vector(1 downto 0); -- sample freq.`
178			`chstat_gstat : in std_logic; -- generation status`
179			`chstat_preem : in std_logic; -- preemphasis status`
180			`chstat_copy : in std_logic; -- copyright bit`
181			`chstat_audio : in std_logic; -- data format`
182			`sample_data : in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data`
183			`mem_rd : out std_logic; -- sample buffer read`
184			`sample_addr : out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- address`
185			`evt_lcsbf : out std_logic; -- lower ch.st./user data buf empty`
186			`evt_hcsbf : out std_logic; -- higher ch.st/user data buf empty`
187			`evt_hsbf : out std_logic; -- higher sample buf empty event`
188			`evt_lsbf : out std_logic; -- lower sample buf empty event`
189			`spdif_tx_o : out std_logic);`
190			`end component;`
191
192	45	gedra	`end tx_package;`

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[/] [spdif_interface/] [trunk/] [rtl/] [vhdl/] [tx_package.vhd] - Blame information for rev 73