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gedra |
/*********************************************************************
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**** ****
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**** WISHBONE SPDIF IP Core ****
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**** ****
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**** This file is part of the SPDIF project ****
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**** http://www.opencores.org/cores/spdif_interface/ ****
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**** ****
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**** Description ****
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**** Definitions for the SPDIF transmitter. ****
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**** ****
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**** ****
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**** To Do: ****
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**** - ****
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**** ****
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**** Author(s): ****
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**** - Geir Drange, gedra@opencores.org ****
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**** ****
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**********************************************************************
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**** ****
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**** Copyright (C) 2004 Authors and OPENCORES.ORG ****
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**** ****
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**** This source file may be used and distributed without ****
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**** restriction provided that this copyright statement is not ****
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**** removed from the file and that any derivative work contains ****
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**** the original copyright notice and the associated disclaimer. ****
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**** ****
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**** This source file is free software; you can redistribute it ****
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**** and/or modify it under the terms of the GNU Lesser General ****
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**** Public License as published by the Free Software Foundation; ****
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**** either version 2.1 of the License, or (at your option) any ****
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**** later version. ****
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**** ****
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**** This source is distributed in the hope that it will be ****
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**** useful, but WITHOUT ANY WARRANTY; without even the implied ****
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**** warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ****
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**** PURPOSE. See the GNU Lesser General Public License for more ****
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**** details. ****
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**** ****
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**** You should have received a copy of the GNU Lesser General ****
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**** Public License along with this source; if not, download it ****
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**** from http://www.opencores.org/lgpl.shtml ****
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**** ****
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**********************************************************************
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**
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** CVS Revision History
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**
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** $Log: not supported by cvs2svn $
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**
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**/
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#ifndef _tx_spdif_
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#define _tx_spdif_
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/*** Register definitions ********************************************/
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#define TX_VERSION 0x00 /* Version register */
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#define TX_CONFIG 0x01 /* Configuration register */
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#define TX_CHSTAT 0x02 /* Channel status control register */
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#define TX_INTMASK 0x03 /* interrupt mask register */
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#define TX_INSTAT 0x04 /* Interrupt event register */
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#define TX_UD_BASE 0x20 /* User data buffer base address */
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#define TX_CS_BASE 0x40 /* Channel status buffer base address */
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#endif
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