This is a simple SPDIF transmitter module written in Verilog.
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This module can either generate its own audio clock by dividing down clk_i or can use an external audio clock to drive the output stream via audio_clk_i.
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For external clocking mode, the audio_clk_i clock rate should be:
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* 32KHz - 4.096MHz
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* 44.1KHz - 5.6448MHz
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* 48KHz - 6.144MHz
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Note that in external clocking mode, the frequency of clk_i must be more than 4 x audio_clk_i frequency.
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For internal clocking mode, the clk_i input is divided to roughly the right frequency required for chosen the sample rate. This isn't going to be exact!
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The input interface expects 32-bits (2 x 16-bit audio samples) to be provided to it on 'sample_i' and held until 'sample_req_o' is pulsed (data pop request).
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This allows connection to a simple FIFO for audio samples.
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##### Testing
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Tested on a Pioneer VSX D510 over TOSLINK and also on a cheap no-brand Ebay D/A converter.
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The supplied testbench requires the SystemC libraries and Icarus Verilog, both of which are available for free.
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##### Configuration
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* CLK_RATE_KHZ - Clock speed (clk_i) in KHz
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* AUDIO_RATE - Audio sample rate, e.g. 44100 or 48000
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* AUDIO_CLK_SRC - Can be INTERNAL or EXTERNAL
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##### Size / Performance
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With the default configuration...
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* the design contains 69 flops, 3 adders, 2 comparators, 11 multiplexers (according to ISE).
