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divadnauj |
-- Proyecto : LOG2 IEEE754
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-- Nombre de archivo : log2_fp.vhd
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-- Titulo : operacion logaritmo en base 2
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-----------------------------------------------------------------------------
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-- Descripcion : calcula el logaritmo en base de dos de un numero en
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-- formato IEEE754.
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--
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-- MANTISBITS : Numero de bits de la mantisa
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-- EXPBITS : Numero de bits del exponente
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-- SEG : Numero de segmentos utilizados para la aproximacion
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-- SEGBITS : Ancho del segmento
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-- i_x : Numero en formato numerico IEEE754
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-- o_log2 : Resultado en formato numerico IEEE754
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-----------------------------------------------------------------------------
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-- Universidad Pedagogica y Tecnologica de Colombia.
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-- Facultad de ingenieria.
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-- Escuela de ingenieria Electronica - extension Tunja.
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--
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-- Autor: Cristhian Fernando Moreno Manrique
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-- Abril 2020
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-----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.log2_pkg.all;
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entity log2_fp is
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generic (MANTISBITS : natural:= 23; -- Formato IEEE754:
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EXPBITS : natural:= 8; -- signo[1] & exponente[8] & mantisa[23]
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SEG : natural:= 64;
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SEGBITS : natural:= 23);
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port (i_x : in std_logic_vector(EXPBITS+MANTISBITS downto 0);
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o_log2 : out std_logic_vector(EXPBITS+MANTISBITS downto 0));
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end entity;
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architecture rtl of log2_fp is
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constant c_64seg_23b : std_logic_vector(SEGBITS-1 downto 0) := "00000000000000000111101";
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constant c_log2_seg : natural := f_log2(SEG);
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signal w_mantis : std_logic_vector(MANTISBITS-1 downto 0);
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signal w_exp : std_logic_vector(EXPBITS-1 downto 0);
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signal w_sgn : std_logic;
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signal w_segment_ctrl : std_logic;
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signal w_lutA_addr : std_logic_vector(c_log2_seg-2 downto 0);
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signal w_lutA_adder : std_logic_vector(c_log2_seg-2 downto 0);
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signal w_lutA : std_logic_vector(SEGBITS-1 downto 0);
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signal w_comp_EQseg : std_logic;
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signal w_mux_lutA_idata : std_logic_vector(2*SEGBITS-1 downto 0);
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--signal w_mux_lutA_isel : std_logic_vector(0 downto 0);
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signal w_mux_lutA : std_logic_vector(SEGBITS-1 downto 0);
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signal w_lutB_addr : std_logic_vector(c_log2_seg-2 downto 0);
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signal w_lutB : std_logic_vector(SEGBITS-1 downto 0);
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signal w_comp_C1_ctrl : std_logic;
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signal w_comp_C1_ctrl_n : std_logic;
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signal w_comp_C1_ctrl_xor : std_logic;
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signal w_comp_C1_ctrl_xnor : std_logic;
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signal w_mux_lutA_C1 : std_logic_vector(SEGBITS-1 downto 0);
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signal w_lutB_C1 : std_logic_vector(SEGBITS-1 downto 0);
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signal w_constants_sub : std_logic_vector(SEGBITS-1 downto 0);
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signal w_muxA_idata : std_logic_vector(2*SEGBITS-1 downto 0);
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--signal w_muxA_iselect : std_logic_vector(0 downto 0);
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signal w_muxA : std_logic_vector(SEGBITS-1 downto 0);
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signal w_adderB : std_logic_vector(SEGBITS-1 downto 0); -- generalizar entradas
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signal w_adderB_cout : std_logic;
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signal w_mantis_decimal : std_logic_vector(MANTISBITS-1 downto 0);
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signal w_mult : std_logic_vector(MANTISBITS*2-1 downto 0);
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signal w_mult_C1_idata : std_logic_vector(MANTISBITS+2 downto 0);
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signal w_mult_C1 : std_logic_vector(MANTISBITS+2 downto 0);
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signal w_adderC_iterm1 : std_logic_vector(MANTISBITS+2 downto 0);
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signal w_adderC : std_logic_vector(MANTISBITS+2 downto 0);
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signal w_exp_comp : std_logic;
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signal w_exp_ncomp : std_logic;
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signal w_adderD : std_logic_vector(EXPBITS-2 downto 0);
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signal w_adderD_C1 : std_logic_vector(EXPBITS-2 downto 0);
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signal w_adderC_C1_idata : std_logic_vector(MANTISBITS+EXPBITS downto 0);
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signal w_adderC_C1 : std_logic_vector(MANTISBITS+EXPBITS downto 0);
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signal w_adderE_iterm2 : std_logic_vector(MANTISBITS+EXPBITS downto 0);
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signal w_adderE : std_logic_vector(MANTISBITS+EXPBITS downto 0);
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signal w_adderE_cout : std_logic;
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signal w_CLZ : std_logic_vector(f_log2(MANTISBITS)-1 downto 0);
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signal w_CLZ_MSB : std_logic;
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signal w_CLZ_adj : std_logic_vector(EXPBITS-2 downto 0);
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signal w_adderE_shift : std_logic_vector(w_adderE'left downto 0);
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signal w_adderF : std_logic_vector(EXPBITS-2 downto 0);
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signal w_coutF : std_logic;
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signal w_mantis_result : std_logic_vector(MANTISBITS-1 downto 0);
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signal w_exp_result : std_logic_vector(EXPBITS-1 downto 0);
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signal w_sgn_result : std_logic;
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signal w_ieeecase : std_logic_vector(i_x'left downto 0);
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signal w_ieeecase_en : std_logic;
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signal w_mux_case_idata : std_logic_vector(i_x'length*2-1 downto 0);
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signal w_mux_case : std_logic_vector(i_x'left downto 0);
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begin
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w_mantis <= i_x(MANTISBITS-1 downto 0);
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w_exp <= i_x(MANTISBITS+EXPBITS-1 downto MANTISBITS);
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w_sgn <= i_x(MANTISBITS+EXPBITS);
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--------------------------------------------------------------------------
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-- < Seleccion de constantes >
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--------------------------------------------------------------------------
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w_lutA_addr <= w_mantis(w_mantis'left downto w_mantis'left-c_log2_seg+2);
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w_lutB_addr <= w_mantis(w_mantis'left downto w_mantis'left-c_log2_seg+2);
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w_segment_ctrl <= w_mantis(w_mantis'left-c_log2_seg+1);
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adder_lutA : entity work.sum_ripple_carry_adder
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generic map(WIDE => c_log2_seg-1)
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port map (i_term1 => w_lutA_addr,
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i_term2 => std_logic_vector(to_unsigned(0, c_log2_seg-1)),
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i_cin => w_segment_ctrl,
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o_sum => w_lutA_adder);
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-- LUT32C: if SEG = 32 generate
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-- LUT32_23b : log2_luts_32x23b
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-- port map (i_lutA_addr => w_lutA_adder,
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-- i_lutB_addr => w_lutB_addr,
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-- o_lutA => w_lutA,
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-- o_lutB => w_lutB);
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-- end generate;
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LUT64C: if SEG = 64 generate
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LUT64_23b : entity work.log2_luts_64x23b
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generic map(SEG=>SEG)
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port map (i_lutA_addr => w_lutA_adder,
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i_lutB_addr => w_lutB_addr,
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o_lutA => w_lutA,
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o_lutB => w_lutB);
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end generate;
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comparator_EQsegments : entity work.comparator
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generic map(WIDE => c_log2_seg,
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MODO => 0)
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port map (i_data1 => w_mantis(w_mantis'left downto MANTISBITS-c_log2_seg),
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i_data2 => std_logic_vector(to_unsigned(SEG-1, c_log2_seg)),
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o_result => w_comp_EQseg);
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--w_mux_lutA_idata <= c_64seg_23b & w_lutA;
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--w_mux_lutA_isel(0) <= w_comp_EQseg & std_logic_vector(to_unsigned(0, 0)); -- entidad mux requiere que el dato siempre sea std_logic_vector
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-- mux_lutA : mux
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-- generic map(SELECT_BITS => 1,
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-- DATA_BITS => SEGBITS)
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-- port map (i_data => w_mux_lutA_idata,
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-- i_select => w_mux_lutA_isel(0),
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-- o_data => w_mux_lutA);
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w_mux_lutA <= w_lutA when w_comp_EQseg='0' else c_64seg_23b;
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--------------------------------------------------------------------------
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-- < control resta de constantes >
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--------------------------------------------------------------------------
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comparator_control_lut : entity work.comparator
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generic map(WIDE => c_log2_seg,
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MODO => 2)
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port map (i_data1 => w_mantis(w_mantis'left downto MANTISBITS-c_log2_seg),
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i_data2 => std_logic_vector(to_unsigned(SEG*7/16, c_log2_seg)), --
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o_result => w_comp_C1_ctrl);
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w_comp_C1_ctrl_n <= not(w_comp_C1_ctrl);
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w_comp_C1_ctrl_xor <= w_comp_C1_ctrl_n xor w_mantis(MANTISBITS-c_log2_seg);
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w_comp_C1_ctrl_xnor <= not(w_comp_C1_ctrl_xor);
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ones_complement_lutA : entity work.ones_complement
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generic map(WIDE => w_mux_lutA'length)
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port map (i_data => w_mux_lutA,
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i_en => w_comp_C1_ctrl_xnor,
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o_data => w_mux_lutA_C1);
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ones_complement_lutB : entity work.ones_complement
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generic map(WIDE => MANTISBITS)
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port map (i_data => w_lutB,
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i_en => w_comp_C1_ctrl_xor,
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o_data => w_lutB_C1);
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constants_sub : entity work.sum_ripple_carry_adder
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generic map(WIDE => MANTISBITS)
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port map (i_term1 => w_mux_lutA_C1,
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i_term2 => w_lutB_C1,
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i_cin => '1',
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o_sum => w_constants_sub);
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--------------------------------------------------------------------------
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-- < Calculo de parte fraccionaria >
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--------------------------------------------------------------------------
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--w_muxA_idata <= w_lutB & w_mux_lutA;
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--w_muxA_iselect <= w_segment_ctrl & std_logic_vector(to_unsigned(0, 0)); -- entidad mux requiere que el dato siempre sea std_logic_vector
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-- muxA : mux
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-- generic map(SELECT_BITS => 1,
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-- DATA_BITS => MANTISBITS)
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-- port map (i_data => w_muxA_idata,
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-- i_select => w_muxA_iselect,
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-- o_data => w_muxA);
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w_muxA <= w_mux_lutA when w_segment_ctrl='0' else w_lutB;
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adderB : entity work.sum_ripple_carry_adder
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generic map(WIDE => MANTISBITS)
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port map (i_term1 => w_muxA,
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i_term2 => w_mantis,
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i_cin => '0',
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o_sum => w_adderB,
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o_cout => w_adderB_cout);
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w_mantis_decimal <= w_mantis(MANTISBITS-c_log2_seg-1 downto 0) & std_logic_vector(to_unsigned(0, c_log2_seg));
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multiplier : entity work.mult
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generic map(WIDE => MANTISBITS)
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port map (i_term1 => w_constants_sub,
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i_term2 => w_mantis_decimal,
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o_product => w_mult);
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w_mult_C1_idata <= "0" & w_mult(MANTISBITS*2-1 downto MANTISBITS-2); -- se añade una parte entera al resultado
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ones_complement_mult : entity work.ones_complement
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generic map(WIDE => w_mult_C1_idata'length)
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port map (i_data => w_mult_C1_idata,
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i_en => w_comp_C1_ctrl_n,
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o_data => w_mult_C1);
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w_adderC_iterm1 <= w_adderB_cout & w_adderB & "00";
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adderC : entity work.sum_ripple_carry_adder
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generic map(WIDE => w_adderC_iterm1'length,
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C1 => 0)
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port map (i_term1 => w_adderC_iterm1,
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i_term2 => w_mult_C1,
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i_cin => w_comp_C1_ctrl_n,
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o_sum => w_adderC);
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--------------------------------------------------------------------------
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-- < calculo de resultado en punto fijo >
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--------------------------------------------------------------------------
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exp_comparator : entity work.comparator
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generic map(WIDE => EXPBITS,
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MODO => 1)
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port map (i_data1 => std_logic_vector(to_unsigned(2**(EXPBITS-1)-1, EXPBITS)),
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i_data2 => w_exp,
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o_result => w_exp_comp);
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w_exp_ncomp <= not(w_exp_comp);
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adderD : entity work.sum_ripple_carry_adder
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generic map(WIDE => EXPBITS-1,
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C1 => 0)
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port map (i_term1 => w_exp(w_exp'left-1 downto 0),
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i_term2 => std_logic_vector(to_unsigned(0, EXPBITS-1)),
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i_cin => w_exp_ncomp,
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o_sum => w_adderD);
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ones_complement_adderD : entity work.ones_complement
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generic map(WIDE => w_adderD'length)
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port map (i_data => w_adderD,
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i_en => w_exp_comp,
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o_data => w_adderD_C1);
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w_adderC_C1_idata <= std_logic_vector(to_unsigned(0, EXPBITS-2)) & w_adderC;
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ones_complement_adderC : entity work.ones_complement
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generic map(WIDE => w_adderC_C1_idata'length)
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port map (i_data => w_adderC_C1_idata,
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i_en => w_exp_comp,
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o_data => w_adderC_C1);
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w_adderE_iterm2 <= w_adderD_C1 & std_logic_vector(to_unsigned(0, MANTISBITS+2));
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adderE : entity work.sum_ripple_carry_adder
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generic map(WIDE => w_adderC_C1'length,
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C1 => 0)
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port map (i_term1 => w_adderC_C1,
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i_term2 => w_adderE_iterm2,
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i_cin => w_exp_comp,
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o_sum => w_adderE);
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--------------------------------------------------------------------------
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-- < calculo de resultado en punto flotante >
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--------------------------------------------------------------------------
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leading_zeros : entity work.CLZ
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301 |
|
|
generic map(MODE => '0',
|
302 |
|
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DATA_BITS => 2**f_log2(w_adderE'length)) -- el modulo solo acepta un ancho de datos 2^x
|
303 |
|
|
port map (i_data => w_adderE,
|
304 |
|
|
o_zeros => w_CLZ,
|
305 |
|
|
o_MSB_zeros => w_CLZ_MSB);
|
306 |
|
|
|
307 |
|
|
shifter : entity work.left_shifter
|
308 |
|
|
generic map(DATA_BITS => w_adderE'length)
|
309 |
|
|
port map (i_data => w_adderE,
|
310 |
|
|
i_shifts => w_CLZ,
|
311 |
|
|
o_dataShift => w_adderE_shift);
|
312 |
|
|
|
313 |
|
|
w_CLZ_adj <= "00" & w_CLZ; -- se añaden ceros segun la cantidad de bits del exponente
|
314 |
|
|
|
315 |
|
|
adderF : entity work.sum_ripple_carry_adder
|
316 |
|
|
generic map(WIDE => EXPBITS-1,
|
317 |
|
|
C1 => 1) -- complemento a 1
|
318 |
|
|
port map (i_term1 => w_CLZ_adj,
|
319 |
|
|
i_term2 => "0000110", -- cte encontrada experimentalmente
|
320 |
|
|
i_cin => '0',
|
321 |
|
|
o_sum => w_adderF,
|
322 |
|
|
o_cout => w_coutF);
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
--------------------------------------------------------------------------
|
326 |
|
|
-- < deteccion de caso ieee>
|
327 |
|
|
--------------------------------------------------------------------------
|
328 |
|
|
|
329 |
|
|
w_sgn_result <= w_exp_comp;
|
330 |
|
|
w_exp_result <= w_coutF & w_adderF;
|
331 |
|
|
w_mantis_result <= w_adderE_shift(w_adderE_shift'left-1 downto w_adderE_shift'left-MANTISBITS);
|
332 |
|
|
|
333 |
|
|
case_ieee32 : entity work.log2_ieee
|
334 |
|
|
port map (i_data => i_x,
|
335 |
|
|
o_case => w_ieeecase,
|
336 |
|
|
o_case_en => w_ieeecase_en);
|
337 |
|
|
|
338 |
|
|
--w_mux_case_idata <= w_ieeecase & w_sgn_result & w_exp_result & w_mantis_result;
|
339 |
|
|
|
340 |
|
|
-- mux_case_select : mux
|
341 |
|
|
-- generic map(SELECT_BITS => 1,
|
342 |
|
|
-- DATA_BITS => i_x'length)
|
343 |
|
|
-- port map (i_data => w_mux_case_idata,
|
344 |
|
|
-- i_select => w_ieeecase_en,
|
345 |
|
|
-- o_data => w_mux_case);
|
346 |
|
|
|
347 |
|
|
w_mux_case <= w_sgn_result & w_exp_result & w_mantis_result when w_ieeecase_en='0' else w_ieeecase;
|
348 |
|
|
|
349 |
|
|
o_log2 <= w_mux_case;
|
350 |
|
|
|
351 |
|
|
end rtl;
|