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[/] [spi/] [tags/] [asyst_3/] [rtl/] [verilog/] [spi_shift.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_shift.v                                                 ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "spi_defines.v"
`include "timescale.v"
 
module spi_shift (clk, rst, latch, len, lsb, go,
                  pos_edge, neg_edge, rx_negedge, tx_negedge,
                  tip, last,
                  p_in, p_out, s_clk, s_in, s_out);
 
  parameter Tp = 1;
 
  input                          clk;          // system clock
  input                          rst;          // reset
  input                    [3:0] latch;        // latch signal for storing the data in shift register
  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
  input                          lsb;          // lbs first on the line
  input                          go;           // start stansfer
  input                          pos_edge;     // recognize posedge of sclk
  input                          neg_edge;     // recognize negedge of sclk
  input                          rx_negedge;   // s_in is sampled on negative edge 
  input                          tx_negedge;   // s_out is driven on negative edge
  output                         tip;          // transfer in progress
  output                         last;         // last bit
  input                   [31:0] p_in;         // parallel in
  output     [`SPI_MAX_CHAR-1:0] p_out;        // parallel out
  input                          s_clk;        // serial clock
  input                          s_in;         // serial in
  output                         s_out;        // serial out
 
  reg                            s_out;
  reg                            tip;
 
  reg     [`SPI_CHAR_LEN_BITS:0] cnt;          // data bit count
  reg        [`SPI_MAX_CHAR-1:0] data;         // shift register
  wire    [`SPI_CHAR_LEN_BITS:0] tx_bit_pos;   // next bit position
  wire    [`SPI_CHAR_LEN_BITS:0] rx_bit_pos;   // next bit position
  wire                           rx_clk;       // rx clock enable
  wire                           tx_clk;       // tx clock enable
 
  assign p_out = data;
 
  assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
  assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
                            (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
 
  assign last = !(|cnt);
 
  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
 
  // Character bit counter
  always @(posedge clk or posedge rst)
  begin
    if(rst)
      cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
    else
      begin
        if(tip)
          cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
        else
          cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
      end
  end
 
  // Transfer in progress
  always @(posedge clk or posedge rst)
  begin
    if(rst)
      tip <= #Tp 1'b0;
  else if(go && ~tip)
    tip <= #Tp 1'b1;
  else if(tip && last && pos_edge)
    tip <= #Tp 1'b0;
  end
 
  // Sending bits to the line
  always @(posedge clk or posedge rst)
  begin
    if (rst)
      s_out   <= #Tp 1'b0;
    else
      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
  end
 
  // Receiving bits from the line
  always @(posedge clk or posedge rst)
  begin
    if (rst)
      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
    else if (latch[0] && !tip)
      data[31:0] <= #Tp p_in[31:0];
    else if (latch[1] && !tip)
      data[63:32] <= #Tp p_in[31:0];
    else if (latch[2] && !tip)
      data[95:64] <= #Tp p_in[31:0];
     else if (latch[3] && !tip)
      data[127:96] <= #Tp p_in[31:0];
`else
`ifdef SPI_MAX_CHAR_64
    else if (latch[0] && !tip)
      data[31:0] <= #Tp p_in[31:0];
    else if (latch[1] && !tip)
      data[63:32] <= #Tp p_in[31:0];
`else
    else if (latch[0] && !tip)
      data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`endif
    else
      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
  end
 
endmodule
 

Line No.	Rev	Author	Line
1	2	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_shift.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			`include "spi_defines.v"
42			`include "timescale.v"
43
44	9	simons	`module spi_shift (clk, rst, latch, len, lsb, go,`
45	2	simons	`pos_edge, neg_edge, rx_negedge, tx_negedge,`
46			`tip, last,`
47			`p_in, p_out, s_clk, s_in, s_out);`
48
49			`parameter Tp = 1;`
50
51			`input clk; // system clock`
52			`input rst; // reset`
53	9	simons	`input [3:0] latch; // latch signal for storing the data in shift register`
54	2	simons	input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
55			`input lsb; // lbs first on the line`
56			`input go; // start stansfer`
57			`input pos_edge; // recognize posedge of sclk`
58			`input neg_edge; // recognize negedge of sclk`
59			`input rx_negedge; // s_in is sampled on negative edge`
60			`input tx_negedge; // s_out is driven on negative edge`
61			`output tip; // transfer in progress`
62			`output last; // last bit`
63	7	simons	`input [31:0] p_in; // parallel in`
64	2	simons	output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
65			`input s_clk; // serial clock`
66			`input s_in; // serial in`
67			`output s_out; // serial out`
68
69			`reg s_out;`
70			`reg tip;`
71
72			reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
73			reg [`SPI_MAX_CHAR-1:0] data; // shift register
74			wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
75			wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
76			`wire rx_clk; // rx clock enable`
77			`wire tx_clk; // tx clock enable`
78
79			`assign p_out = data;`
80
81			assign tx_bit_pos = lsb ? {!(\|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
82			assign rx_bit_pos = lsb ? {!(\|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
83			(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
84
85			`assign last = !(\|cnt);`
86
87			`assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last \|\| s_clk);`
88			`assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;`
89
90			`// Character bit counter`
91			`always @(posedge clk or posedge rst)`
92			`begin`
93			`if(rst)`
94			cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
95			`else`
96			`begin`
97			`if(tip)`
98			cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
99			`else`
100			cnt <= #Tp !(\|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
101			`end`
102			`end`
103
104			`// Transfer in progress`
105			`always @(posedge clk or posedge rst)`
106			`begin`
107			`if(rst)`
108			`tip <= #Tp 1'b0;`
109			`else if(go && ~tip)`
110			`tip <= #Tp 1'b1;`
111			`else if(tip && last && pos_edge)`
112			`tip <= #Tp 1'b0;`
113			`end`
114
115			`// Sending bits to the line`
116			`always @(posedge clk or posedge rst)`
117			`begin`
118			`if (rst)`
119			`s_out <= #Tp 1'b0;`
120			`else`
121			s_out <= #Tp (tx_clk \|\| !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
122			`end`
123
124			`// Receiving bits from the line`
125			`always @(posedge clk or posedge rst)`
126			`begin`
127			`if (rst)`
128			data <= #Tp {`SPI_MAX_CHAR{1'b0}};
129	9	simons	`ifdef SPI_MAX_CHAR_128
130			`else if (latch[0] && !tip)`
131			`data[31:0] <= #Tp p_in[31:0];`
132			`else if (latch[1] && !tip)`
133			`data[63:32] <= #Tp p_in[31:0];`
134			`else if (latch[2] && !tip)`
135			`data[95:64] <= #Tp p_in[31:0];`
136			`else if (latch[3] && !tip)`
137			`data[127:96] <= #Tp p_in[31:0];`
138			`else
139	7	simons	`ifdef SPI_MAX_CHAR_64
140	9	simons	`else if (latch[0] && !tip)`
141	7	simons	`data[31:0] <= #Tp p_in[31:0];`
142	9	simons	`else if (latch[1] && !tip)`
143	7	simons	`data[63:32] <= #Tp p_in[31:0];`
144			`else
145	9	simons	`else if (latch[0] && !tip)`
146	7	simons	data <= #Tp p_in[`SPI_MAX_CHAR-1:0];
147			`endif
148	9	simons	`endif
149	2	simons	`else`
150			data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
151			`end`
152
153			`endmodule`
154

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[/] [spi/] [tags/] [asyst_3/] [rtl/] [verilog/] [spi_shift.v] - Blame information for rev 9