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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tb_spi_top.v                                                ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  Based on:                                                   ////
////      - i2c/bench/verilog/tst_bench_top.v                     ////
////        Copyright (C) 2001 Richard Herveille                  ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module tb_spi_top();
 
  reg         clk;
  reg         rst;
  wire [31:0] adr;
  wire [31:0] dat_i, dat_o;
  wire        we;
  wire  [3:0] sel;
  wire        stb;
  wire        cyc;
  wire        ack;
  wire        err;
  wire        int;
 
  wire  [7:0] ss;
  wire        sclk;
  wire        mosi;
  wire        miso;
 
  reg  [31:0] q;
  reg  [31:0] q1;
  reg  [31:0] q2;
  reg  [31:0] q3;
 
  parameter SPI_RX_0   = 5'h0;
  parameter SPI_RX_1   = 5'h4;
  parameter SPI_RX_2   = 5'h8;
  parameter SPI_RX_3   = 5'hc;
  parameter SPI_TX_0   = 5'h0;
  parameter SPI_TX_1   = 5'h4;
  parameter SPI_TX_2   = 5'h8;
  parameter SPI_TX_3   = 5'hc;
  parameter SPI_CTRL   = 5'h10;
  parameter SPI_DIVIDE = 5'h14;
  parameter SPI_SS     = 5'h18;
 
  // Generate clock
  always #5 clk = ~clk;
 
  // Wishbone master model
  wb_master_model #(32, 32) i_wb_master (
    .clk(clk), .rst(rst),
    .adr(adr), .din(dat_i), .dout(dat_o),
    .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0)
  );
 
  // SPI master core
  spi_top i_spi_top (
    .wb_clk_i(clk), .wb_rst_i(rst),
    .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i),
    .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb),
    .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int),
    .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)
  );
 
  // SPI slave model
  spi_slave_model i_spi_slave (
    .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso)
  );
 
  initial
    begin
      $display("\nstatus: %t Testbench started\n\n", $time);
 
      $dumpfile("bench.vcd");
      $dumpvars(1, tb_spi_top);
      $dumpvars(1, tb_spi_top.i_spi_slave);
 
      // Initial values
      clk = 0;
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b0;
 
      // Reset system
      rst = 1'b0; // negate reset
      #2;
      rst = 1'b1; // assert reset
      repeat(20) @(posedge clk);
      rst = 1'b0; // negate reset
 
      $display("status: %t done reset", $time);
 
      @(posedge clk);
 
      // Program core
      i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register
      i_wb_master.wb_write(0, SPI_TX_0, 32'h5a);   // set tx register to 0x5a
      i_wb_master.wb_write(0, SPI_CTRL, 32'h42);   // set 8 bit transfer
      i_wb_master.wb_write(0, SPI_SS, 32'h01);     // set ss 0
 
      $display("status: %t programmed registers", $time);
 
      i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h05);   // verify devider register
      i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a);     // verify tx register
      i_wb_master.wb_cmp(0, SPI_CTRL, 32'h42);     // verify tx register
      i_wb_master.wb_cmp(0, SPI_SS, 32'h01);       // verify ss register
 
      $display("status: %t verified registers", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_spi_slave.data[31:0] = 32'ha5967e5a;
      i_wb_master.wb_write(0, SPI_CTRL, 32'h43);   // set 8 bit transfer, start transfer
 
      $display("status: %t generate transfer:  8 bit, msb first, tx posedge, rx negedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[0])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
 
      if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h44);   // set 8 bit transfer, tx negedge
      i_wb_master.wb_write(0, SPI_CTRL, 32'h45);   // set 8 bit transfer, tx negedge, start transfer
 
      $display("status: %t generate transfer:  8 bit, msb first, tx negedge, rx posedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[0])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
 
      if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h484);   // set 16 bit transfer, tx negedge, lsb
      i_wb_master.wb_write(0, SPI_CTRL, 32'h485);   // set 16 bit transfer, tx negedge, start transfer
 
      $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[0])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
 
      if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);
      i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h602);   // set 64 bit transfer, rx negedge, lsb
      i_wb_master.wb_write(0, SPI_CTRL, 32'h603);   // set 64 bit transfer, rx negedge, start transfer
 
      $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[0])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      i_wb_master.wb_read(1, SPI_RX_1, q1);
 
      if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff);
      i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);
      i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);
      i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h04);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h05);
 
      $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[0])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      i_wb_master.wb_read(1, SPI_RX_1, q1);
      i_wb_master.wb_read(1, SPI_RX_2, q2);
      i_wb_master.wb_read(1, SPI_RX_3, q3);
 
      if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h904);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h905);
 
      $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);
 
      // Check interrupt signal
      while (!int)
        @(posedge clk);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
 
      @(posedge clk);
      if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h1902);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h1903);
 
      $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
 
      while (!int)
        @(posedge clk);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
 
      @(posedge clk);
      if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h1);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h180a);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h180b);
 
      $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
 
      while (!int)
        @(posedge clk);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
 
      @(posedge clk);
      if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      $display("\n\nstatus: %t Testbench done", $time);
 
      #25000; // wait 25us
 
      $stop;
    end
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tb_spi_top.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// Based on: ////`
12			`//// - i2c/bench/verilog/tst_bench_top.v ////`
13			`//// Copyright (C) 2001 Richard Herveille ////`
14			`//// ////`
15			`//// All additional information is avaliable in the Readme.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`module tb_spi_top();`
48
49			`reg clk;`
50			`reg rst;`
51			`wire [31:0] adr;`
52			`wire [31:0] dat_i, dat_o;`
53			`wire we;`
54			`wire [3:0] sel;`
55			`wire stb;`
56			`wire cyc;`
57			`wire ack;`
58			`wire err;`
59			`wire int;`
60
61			`wire [7:0] ss;`
62			`wire sclk;`
63			`wire mosi;`
64			`wire miso;`
65
66			`reg [31:0] q;`
67	9	simons	`reg [31:0] q1;`
68			`reg [31:0] q2;`
69			`reg [31:0] q3;`
70	2	simons
71	9	simons	`parameter SPI_RX_0 = 5'h0;`
72			`parameter SPI_RX_1 = 5'h4;`
73			`parameter SPI_RX_2 = 5'h8;`
74			`parameter SPI_RX_3 = 5'hc;`
75			`parameter SPI_TX_0 = 5'h0;`
76			`parameter SPI_TX_1 = 5'h4;`
77			`parameter SPI_TX_2 = 5'h8;`
78			`parameter SPI_TX_3 = 5'hc;`
79			`parameter SPI_CTRL = 5'h10;`
80			`parameter SPI_DIVIDE = 5'h14;`
81			`parameter SPI_SS = 5'h18;`
82	2	simons
83			`// Generate clock`
84			`always #5 clk = ~clk;`
85
86			`// Wishbone master model`
87			`wb_master_model #(32, 32) i_wb_master (`
88			`.clk(clk), .rst(rst),`
89			`.adr(adr), .din(dat_i), .dout(dat_o),`
90			`.cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0)`
91			`);`
92
93			`// SPI master core`
94			`spi_top i_spi_top (`
95			`.wb_clk_i(clk), .wb_rst_i(rst),`
96			`.wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i),`
97			`.wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb),`
98			`.wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int),`
99			`.ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)`
100			`);`
101
102			`// SPI slave model`
103			`spi_slave_model i_spi_slave (`
104			`.rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso)`
105			`);`
106
107			`initial`
108			`begin`
109			`$display("\nstatus: %t Testbench started\n\n", $time);`
110
111			`$dumpfile("bench.vcd");`
112			`$dumpvars(1, tb_spi_top);`
113			`$dumpvars(1, tb_spi_top.i_spi_slave);`
114
115			`// Initial values`
116			`clk = 0;`
117
118			`i_spi_slave.rx_negedge = 1'b0;`
119			`i_spi_slave.tx_negedge = 1'b0;`
120
121			`// Reset system`
122			`rst = 1'b0; // negate reset`
123			`#2;`
124			`rst = 1'b1; // assert reset`
125			`repeat(20) @(posedge clk);`
126			`rst = 1'b0; // negate reset`
127
128			`$display("status: %t done reset", $time);`
129
130			`@(posedge clk);`
131
132			`// Program core`
133	9	simons	`i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register`
134			`i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a`
135			`i_wb_master.wb_write(0, SPI_CTRL, 32'h42); // set 8 bit transfer`
136	2	simons	`i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0`
137
138			`$display("status: %t programmed registers", $time);`
139
140	9	simons	`i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h05); // verify devider register`
141			`i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register`
142			`i_wb_master.wb_cmp(0, SPI_CTRL, 32'h42); // verify tx register`
143	2	simons	`i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register`
144
145			`$display("status: %t verified registers", $time);`
146
147			`i_spi_slave.rx_negedge = 1'b1;`
148	9	simons	`i_spi_slave.tx_negedge = 1'b0;`
149			`i_spi_slave.data[31:0] = 32'ha5967e5a;`
150			`i_wb_master.wb_write(0, SPI_CTRL, 32'h43); // set 8 bit transfer, start transfer`
151	2	simons
152	9	simons	`$display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time);`
153	2	simons
154			`// Check bsy bit`
155			`i_wb_master.wb_read(0, SPI_CTRL, q);`
156			`while (q[0])`
157			`i_wb_master.wb_read(1, SPI_CTRL, q);`
158
159	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
160
161			`if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)`
162			`$display("status: %t transfer completed: ok", $time);`
163	2	simons	`else`
164	9	simons	`$display("status: %t transfer completed: nok", $time);`
165	2	simons
166			`i_spi_slave.rx_negedge = 1'b0;`
167	9	simons	`i_spi_slave.tx_negedge = 1'b1;`
168			`i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);`
169	2	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h44); // set 8 bit transfer, tx negedge`
170			`i_wb_master.wb_write(0, SPI_CTRL, 32'h45); // set 8 bit transfer, tx negedge, start transfer`
171
172	9	simons	`$display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time);`
173	2	simons
174			`// Check bsy bit`
175			`i_wb_master.wb_read(0, SPI_CTRL, q);`
176			`while (q[0])`
177			`i_wb_master.wb_read(1, SPI_CTRL, q);`
178
179	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
180	2	simons
181	9	simons	`if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)`
182			`$display("status: %t transfer completed: ok", $time);`
183	2	simons	`else`
184	9	simons	`$display("status: %t transfer completed: nok", $time);`
185	2	simons
186			`i_spi_slave.rx_negedge = 1'b0;`
187			`i_spi_slave.tx_negedge = 1'b1;`
188	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);`
189			`i_wb_master.wb_write(0, SPI_CTRL, 32'h484); // set 16 bit transfer, tx negedge, lsb`
190			`i_wb_master.wb_write(0, SPI_CTRL, 32'h485); // set 16 bit transfer, tx negedge, start transfer`
191	2	simons
192	9	simons	`$display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);`
193	2	simons
194			`// Check bsy bit`
195			`i_wb_master.wb_read(0, SPI_CTRL, q);`
196			`while (q[0])`
197			`i_wb_master.wb_read(1, SPI_CTRL, q);`
198
199	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
200	2	simons
201	9	simons	`if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)`
202			`$display("status: %t transfer completed: ok", $time);`
203	2	simons	`else`
204	9	simons	`$display("status: %t transfer completed: nok", $time);`
205	2	simons
206			`i_spi_slave.rx_negedge = 1'b1;`
207			`i_spi_slave.tx_negedge = 1'b0;`
208	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);`
209			`i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);`
210			`i_wb_master.wb_write(0, SPI_CTRL, 32'h602); // set 64 bit transfer, rx negedge, lsb`
211			`i_wb_master.wb_write(0, SPI_CTRL, 32'h603); // set 64 bit transfer, rx negedge, start transfer`
212	2	simons
213	9	simons	`$display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);`
214	2	simons
215			`// Check bsy bit`
216			`i_wb_master.wb_read(0, SPI_CTRL, q);`
217			`while (q[0])`
218			`i_wb_master.wb_read(1, SPI_CTRL, q);`
219
220	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
221			`i_wb_master.wb_read(1, SPI_RX_1, q1);`
222	2	simons
223	9	simons	`if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)`
224			`$display("status: %t transfer completed: ok", $time);`
225	2	simons	`else`
226	9	simons	`$display("status: %t transfer completed: nok", $time);`
227	2	simons
228	9	simons	`i_spi_slave.rx_negedge = 1'b0;`
229			`i_spi_slave.tx_negedge = 1'b1;`
230			`i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff);`
231			`i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);`
232			`i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);`
233			`i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);`
234			`i_wb_master.wb_write(0, SPI_CTRL, 32'h04);`
235			`i_wb_master.wb_write(0, SPI_CTRL, 32'h05);`
236	2	simons
237	9	simons	`$display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);`
238	2	simons
239			`// Check bsy bit`
240			`i_wb_master.wb_read(0, SPI_CTRL, q);`
241			`while (q[0])`
242			`i_wb_master.wb_read(1, SPI_CTRL, q);`
243
244	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
245			`i_wb_master.wb_read(1, SPI_RX_1, q1);`
246			`i_wb_master.wb_read(1, SPI_RX_2, q2);`
247			`i_wb_master.wb_read(1, SPI_RX_3, q3);`
248	2	simons
249	9	simons	`if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)`
250			`$display("status: %t transfer completed: ok", $time);`
251	2	simons	`else`
252	9	simons	`$display("status: %t transfer completed: nok", $time);`
253	2	simons
254	9	simons	`i_spi_slave.rx_negedge = 1'b0;`
255	2	simons	`i_spi_slave.tx_negedge = 1'b1;`
256	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);`
257			`i_wb_master.wb_write(0, SPI_CTRL, 32'h904);`
258			`i_wb_master.wb_write(0, SPI_CTRL, 32'h905);`
259	2	simons
260	9	simons	`$display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);`
261	2	simons
262			`// Check interrupt signal`
263			`while (!int)`
264			`@(posedge clk);`
265
266	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
267	2	simons
268			`@(posedge clk);`
269	9	simons	`if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)`
270			`$display("status: %t transfer completed: ok", $time);`
271	2	simons	`else`
272	9	simons	`$display("status: %t transfer completed: nok", $time);`
273	2	simons
274	9	simons	`i_spi_slave.rx_negedge = 1'b1;`
275	2	simons	`i_spi_slave.tx_negedge = 1'b0;`
276	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);`
277			`i_wb_master.wb_write(0, SPI_CTRL, 32'h1902);`
278			`i_wb_master.wb_write(0, SPI_CTRL, 32'h1903);`
279	2	simons
280	9	simons	`$display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);`
281	2	simons
282			`while (!int)`
283			`@(posedge clk);`
284
285	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
286	2	simons
287			`@(posedge clk);`
288	9	simons	`if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)`
289			`$display("status: %t transfer completed: ok", $time);`
290	2	simons	`else`
291	9	simons	`$display("status: %t transfer completed: nok", $time);`
292	2	simons
293	9	simons	`i_spi_slave.rx_negedge = 1'b1;`
294			`i_spi_slave.tx_negedge = 1'b0;`
295			`i_wb_master.wb_write(0, SPI_TX_0, 32'h1);`
296			`i_wb_master.wb_write(0, SPI_CTRL, 32'h180a);`
297			`i_wb_master.wb_write(0, SPI_CTRL, 32'h180b);`
298	7	simons
299	9	simons	`$display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);`
300	7	simons
301			`while (!int)`
302			`@(posedge clk);`
303
304	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
305	7	simons
306			`@(posedge clk);`
307	9	simons	`if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)`
308			`$display("status: %t transfer completed: ok", $time);`
309	7	simons	`else`
310	9	simons	`$display("status: %t transfer completed: nok", $time);`
311	7	simons
312	2	simons	`$display("\n\nstatus: %t Testbench done", $time);`
313
314			`#25000; // wait 25us`
315
316			`$stop;`
317			`end`
318
319			`endmodule`
320
321

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