URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [tags/] [rel_7/] [sim/] [run/] [sim] - Blame information for rev 27

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ncprep \
  ../../bench/verilog/tb_spi_top.v \
  ../../bench/verilog/wb_master_model.v \
  ../../bench/verilog/spi_slave_model.v \
  ../../rtl/verilog/spi_top.v \
  ../../rtl/verilog/spi_clgen.v \
  ../../rtl/verilog/spi_shift.v \
  +incdir+../../rtl/verilog/ \
  +mess \
  +access+r \
  +notimingchecks \
  +overwrite \
  +ncsimargs+"-errormax 10" \
  +tcl+"./tcl.scr"

Line No.	Rev	Author	Line
1	2	simons	`ncprep \`
2			`../../bench/verilog/tb_spi_top.v \`
3			`../../bench/verilog/wb_master_model.v \`
4			`../../bench/verilog/spi_slave_model.v \`
5			`../../rtl/verilog/spi_top.v \`
6			`../../rtl/verilog/spi_clgen.v \`
7			`../../rtl/verilog/spi_shift.v \`
8			`+incdir+../../rtl/verilog/ \`
9			`+mess \`
10			`+access+r \`
11			`+notimingchecks \`
12			`+overwrite \`
13			`+ncsimargs+"-errormax 10" \`
14			`+tcl+"./tcl.scr"`

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Subversion Repositories spi

[/] [spi/] [tags/] [rel_7/] [sim/] [run/] [sim] - Blame information for rev 27