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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  tb_spi_top.v                                                ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  Based on:                                                   ////
////      - i2c/bench/verilog/tst_bench_top.v                     ////
////        Copyright (C) 2001 Richard Herveille                  ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
module tb_spi_top();
 
  reg         clk;
  reg         rst;
  wire [31:0] adr;
  wire [31:0] dat_i, dat_o;
  wire        we;
  wire  [3:0] sel;
  wire        stb;
  wire        cyc;
  wire        ack;
  wire        err;
  wire        int;
 
  wire  [7:0] ss;
  wire        sclk;
  wire        mosi;
  wire        miso;
 
  reg  [31:0] q;
  reg  [31:0] q1;
  reg  [31:0] q2;
  reg  [31:0] q3;
  reg  [31:0] result;
 
  parameter SPI_RX_0   = 5'h0;
  parameter SPI_RX_1   = 5'h4;
  parameter SPI_RX_2   = 5'h8;
  parameter SPI_RX_3   = 5'hc;
  parameter SPI_TX_0   = 5'h0;
  parameter SPI_TX_1   = 5'h4;
  parameter SPI_TX_2   = 5'h8;
  parameter SPI_TX_3   = 5'hc;
  parameter SPI_CTRL   = 5'h10;
  parameter SPI_DIVIDE = 5'h14;
  parameter SPI_SS     = 5'h18;
 
  // Generate clock
  always #5 clk = ~clk;
 
  // Wishbone master model
  wb_master_model #(32, 32) i_wb_master (
    .clk(clk), .rst(rst),
    .adr(adr), .din(dat_i), .dout(dat_o),
    .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0)
  );
 
  // SPI master core
  spi_top i_spi_top (
    .wb_clk_i(clk), .wb_rst_i(rst),
    .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i),
    .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb),
    .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int),
    .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)
  );
 
  // SPI slave model
  spi_slave_model i_spi_slave (
    .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso)
  );
 
  initial
    begin
      $display("\nstatus: %t Testbench started\n\n", $time);
 
      $dumpfile("bench.vcd");
      $dumpvars(1, tb_spi_top);
      $dumpvars(1, tb_spi_top.i_spi_slave);
 
      // Initial values
      clk = 0;
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b0;
 
      result = 32'h0;
 
      // Reset system
      rst = 1'b0; // negate reset
      #2;
      rst = 1'b1; // assert reset
      repeat(20) @(posedge clk);
      rst = 1'b0; // negate reset
 
      $display("status: %t done reset", $time);
 
      @(posedge clk);
 
      // Program core
      i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register
      i_wb_master.wb_write(0, SPI_TX_0, 32'h5a);   // set tx register to 0x5a
      i_wb_master.wb_write(0, SPI_CTRL, 32'h208);   // set 8 bit transfer
      i_wb_master.wb_write(0, SPI_SS, 32'h01);     // set ss 0
 
      $display("status: %t programmed registers", $time);
 
      i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00);   // verify devider register
      i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a);     // verify tx register
      i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208);     // verify tx register
      i_wb_master.wb_cmp(0, SPI_SS, 32'h01);       // verify ss register
 
      $display("status: %t verified registers", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_spi_slave.data[31:0] = 32'ha5967e5a;
      i_wb_master.wb_write(0, SPI_CTRL, 32'h308);   // set 8 bit transfer, start transfer
 
      $display("status: %t generate transfer:  8 bit, msb first, tx posedge, rx negedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[8])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
 
      if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h408);   // set 8 bit transfer, tx negedge
      i_wb_master.wb_write(0, SPI_CTRL, 32'h508);   // set 8 bit transfer, tx negedge, start transfer
 
      $display("status: %t generate transfer:  8 bit, msb first, tx negedge, rx posedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[8])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
 
      if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);
      i_wb_master.wb_write(0, SPI_CTRL, 32'hc10);   // set 16 bit transfer, tx negedge, lsb
      i_wb_master.wb_write(0, SPI_CTRL, 32'hd10);   // set 16 bit transfer, tx negedge, start transfer
 
      $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[8])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
 
      if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);
      i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40);   // set 64 bit transfer, rx negedge, lsb
      i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40);   // set 64 bit transfer, rx negedge, start transfer
 
      $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[8])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
      i_wb_master.wb_read(1, SPI_RX_1, q1);
      result = result + q1;
 
      if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff);
      i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);
      i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);
      i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h400);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h500);
 
      $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);
 
      // Check bsy bit
      i_wb_master.wb_read(0, SPI_CTRL, q);
      while (q[8])
        i_wb_master.wb_read(1, SPI_CTRL, q);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
      i_wb_master.wb_read(1, SPI_RX_1, q1);
      result = result + q1;
      i_wb_master.wb_read(1, SPI_RX_2, q2);
      result = result + q2;
      i_wb_master.wb_read(1, SPI_RX_3, q3);
      result = result + q3;
 
      if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b0;
      i_spi_slave.tx_negedge = 1'b1;
      i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h1420);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h1520);
 
      $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);
 
      // Check interrupt signal
      while (!int)
        @(posedge clk);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
 
      @(posedge clk);
      if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h3220);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h3320);
 
      $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
 
      while (!int)
        @(posedge clk);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
 
      @(posedge clk);
      if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      i_spi_slave.rx_negedge = 1'b1;
      i_spi_slave.tx_negedge = 1'b0;
      i_wb_master.wb_write(0, SPI_TX_0, 32'h1);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h3201);
      i_wb_master.wb_write(0, SPI_CTRL, 32'h3301);
 
      $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
 
      while (!int)
        @(posedge clk);
 
      i_wb_master.wb_read(1, SPI_RX_0, q);
      result = result + q;
 
      @(posedge clk);
      if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)
        $display("status: %t transfer completed: ok", $time);
      else
        $display("status: %t transfer completed: nok", $time);
 
      $display("\n\nstatus: %t Testbench done", $time);
 
      #25000; // wait 25us
 
      $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead);
      $display("exit (%h)", result ^ 32'h2e8b36ab);
 
      $stop;
    end
 
endmodule
 
 

Line No.	Rev	Author	Line
1	2	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// tb_spi_top.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// Based on: ////`
12			`//// - i2c/bench/verilog/tst_bench_top.v ////`
13			`//// Copyright (C) 2001 Richard Herveille ////`
14			`//// ////`
15			`//// All additional information is avaliable in the Readme.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44
45			`include "timescale.v"
46
47			`module tb_spi_top();`
48
49			`reg clk;`
50			`reg rst;`
51			`wire [31:0] adr;`
52			`wire [31:0] dat_i, dat_o;`
53			`wire we;`
54			`wire [3:0] sel;`
55			`wire stb;`
56			`wire cyc;`
57			`wire ack;`
58			`wire err;`
59			`wire int;`
60
61			`wire [7:0] ss;`
62			`wire sclk;`
63			`wire mosi;`
64			`wire miso;`
65
66			`reg [31:0] q;`
67	9	simons	`reg [31:0] q1;`
68			`reg [31:0] q2;`
69			`reg [31:0] q3;`
70	25	simons	`reg [31:0] result;`
71	2	simons
72	9	simons	`parameter SPI_RX_0 = 5'h0;`
73			`parameter SPI_RX_1 = 5'h4;`
74			`parameter SPI_RX_2 = 5'h8;`
75			`parameter SPI_RX_3 = 5'hc;`
76			`parameter SPI_TX_0 = 5'h0;`
77			`parameter SPI_TX_1 = 5'h4;`
78			`parameter SPI_TX_2 = 5'h8;`
79			`parameter SPI_TX_3 = 5'hc;`
80			`parameter SPI_CTRL = 5'h10;`
81			`parameter SPI_DIVIDE = 5'h14;`
82			`parameter SPI_SS = 5'h18;`
83	2	simons
84			`// Generate clock`
85			`always #5 clk = ~clk;`
86
87			`// Wishbone master model`
88			`wb_master_model #(32, 32) i_wb_master (`
89			`.clk(clk), .rst(rst),`
90			`.adr(adr), .din(dat_i), .dout(dat_o),`
91			`.cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0)`
92			`);`
93
94			`// SPI master core`
95			`spi_top i_spi_top (`
96			`.wb_clk_i(clk), .wb_rst_i(rst),`
97			`.wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i),`
98			`.wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb),`
99			`.wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int),`
100			`.ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso)`
101			`);`
102
103			`// SPI slave model`
104			`spi_slave_model i_spi_slave (`
105			`.rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso)`
106			`);`
107
108			`initial`
109			`begin`
110			`$display("\nstatus: %t Testbench started\n\n", $time);`
111
112			`$dumpfile("bench.vcd");`
113			`$dumpvars(1, tb_spi_top);`
114			`$dumpvars(1, tb_spi_top.i_spi_slave);`
115
116			`// Initial values`
117			`clk = 0;`
118
119			`i_spi_slave.rx_negedge = 1'b0;`
120			`i_spi_slave.tx_negedge = 1'b0;`
121
122	25	simons	`result = 32'h0;`
123
124	2	simons	`// Reset system`
125			`rst = 1'b0; // negate reset`
126			`#2;`
127			`rst = 1'b1; // assert reset`
128			`repeat(20) @(posedge clk);`
129			`rst = 1'b0; // negate reset`
130
131			`$display("status: %t done reset", $time);`
132
133			`@(posedge clk);`
134
135			`// Program core`
136	9	simons	`i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register`
137			`i_wb_master.wb_write(0, SPI_TX_0, 32'h5a); // set tx register to 0x5a`
138	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h208); // set 8 bit transfer`
139	2	simons	`i_wb_master.wb_write(0, SPI_SS, 32'h01); // set ss 0`
140
141			`$display("status: %t programmed registers", $time);`
142
143	12	simons	`i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00); // verify devider register`
144	9	simons	`i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a); // verify tx register`
145	25	simons	`i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208); // verify tx register`
146	2	simons	`i_wb_master.wb_cmp(0, SPI_SS, 32'h01); // verify ss register`
147
148			`$display("status: %t verified registers", $time);`
149
150			`i_spi_slave.rx_negedge = 1'b1;`
151	9	simons	`i_spi_slave.tx_negedge = 1'b0;`
152			`i_spi_slave.data[31:0] = 32'ha5967e5a;`
153	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h308); // set 8 bit transfer, start transfer`
154	2	simons
155	9	simons	`$display("status: %t generate transfer: 8 bit, msb first, tx posedge, rx negedge", $time);`
156	2	simons
157			`// Check bsy bit`
158			`i_wb_master.wb_read(0, SPI_CTRL, q);`
159	25	simons	`while (q[8])`
160	2	simons	`i_wb_master.wb_read(1, SPI_CTRL, q);`
161
162	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
163	25	simons	`result = result + q;`
164	9	simons
165			`if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)`
166			`$display("status: %t transfer completed: ok", $time);`
167	2	simons	`else`
168	9	simons	`$display("status: %t transfer completed: nok", $time);`
169	2	simons
170			`i_spi_slave.rx_negedge = 1'b0;`
171	9	simons	`i_spi_slave.tx_negedge = 1'b1;`
172			`i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);`
173	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h408); // set 8 bit transfer, tx negedge`
174			`i_wb_master.wb_write(0, SPI_CTRL, 32'h508); // set 8 bit transfer, tx negedge, start transfer`
175	2	simons
176	9	simons	`$display("status: %t generate transfer: 8 bit, msb first, tx negedge, rx posedge", $time);`
177	2	simons
178			`// Check bsy bit`
179			`i_wb_master.wb_read(0, SPI_CTRL, q);`
180	25	simons	`while (q[8])`
181	2	simons	`i_wb_master.wb_read(1, SPI_CTRL, q);`
182
183	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
184	25	simons	`result = result + q;`
185	2	simons
186	9	simons	`if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)`
187			`$display("status: %t transfer completed: ok", $time);`
188	2	simons	`else`
189	9	simons	`$display("status: %t transfer completed: nok", $time);`
190	2	simons
191			`i_spi_slave.rx_negedge = 1'b0;`
192			`i_spi_slave.tx_negedge = 1'b1;`
193	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);`
194	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'hc10); // set 16 bit transfer, tx negedge, lsb`
195			`i_wb_master.wb_write(0, SPI_CTRL, 32'hd10); // set 16 bit transfer, tx negedge, start transfer`
196	2	simons
197	9	simons	`$display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);`
198	2	simons
199			`// Check bsy bit`
200			`i_wb_master.wb_read(0, SPI_CTRL, q);`
201	25	simons	`while (q[8])`
202	2	simons	`i_wb_master.wb_read(1, SPI_CTRL, q);`
203
204	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
205	25	simons	`result = result + q;`
206	2	simons
207	9	simons	`if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)`
208			`$display("status: %t transfer completed: ok", $time);`
209	2	simons	`else`
210	9	simons	`$display("status: %t transfer completed: nok", $time);`
211	2	simons
212			`i_spi_slave.rx_negedge = 1'b1;`
213			`i_spi_slave.tx_negedge = 1'b0;`
214	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);`
215			`i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);`
216	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40); // set 64 bit transfer, rx negedge, lsb`
217			`i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40); // set 64 bit transfer, rx negedge, start transfer`
218	2	simons
219	9	simons	`$display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);`
220	2	simons
221			`// Check bsy bit`
222			`i_wb_master.wb_read(0, SPI_CTRL, q);`
223	25	simons	`while (q[8])`
224	2	simons	`i_wb_master.wb_read(1, SPI_CTRL, q);`
225
226	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
227	25	simons	`result = result + q;`
228	9	simons	`i_wb_master.wb_read(1, SPI_RX_1, q1);`
229	25	simons	`result = result + q1;`
230	2	simons
231	9	simons	`if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)`
232			`$display("status: %t transfer completed: ok", $time);`
233	2	simons	`else`
234	9	simons	`$display("status: %t transfer completed: nok", $time);`
235	2	simons
236	9	simons	`i_spi_slave.rx_negedge = 1'b0;`
237			`i_spi_slave.tx_negedge = 1'b1;`
238			`i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff);`
239			`i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);`
240			`i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);`
241			`i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);`
242	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h400);`
243			`i_wb_master.wb_write(0, SPI_CTRL, 32'h500);`
244	2	simons
245	9	simons	`$display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);`
246	2	simons
247			`// Check bsy bit`
248			`i_wb_master.wb_read(0, SPI_CTRL, q);`
249	25	simons	`while (q[8])`
250	2	simons	`i_wb_master.wb_read(1, SPI_CTRL, q);`
251
252	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
253	25	simons	`result = result + q;`
254	9	simons	`i_wb_master.wb_read(1, SPI_RX_1, q1);`
255	25	simons	`result = result + q1;`
256	9	simons	`i_wb_master.wb_read(1, SPI_RX_2, q2);`
257	25	simons	`result = result + q2;`
258	9	simons	`i_wb_master.wb_read(1, SPI_RX_3, q3);`
259	25	simons	`result = result + q3;`
260	2	simons
261	9	simons	`if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)`
262			`$display("status: %t transfer completed: ok", $time);`
263	2	simons	`else`
264	9	simons	`$display("status: %t transfer completed: nok", $time);`
265	2	simons
266	9	simons	`i_spi_slave.rx_negedge = 1'b0;`
267	2	simons	`i_spi_slave.tx_negedge = 1'b1;`
268	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);`
269	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h1420);`
270			`i_wb_master.wb_write(0, SPI_CTRL, 32'h1520);`
271	2	simons
272	9	simons	`$display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);`
273	2	simons
274			`// Check interrupt signal`
275			`while (!int)`
276			`@(posedge clk);`
277
278	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
279	25	simons	`result = result + q;`
280	2	simons
281			`@(posedge clk);`
282	9	simons	`if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)`
283			`$display("status: %t transfer completed: ok", $time);`
284	2	simons	`else`
285	9	simons	`$display("status: %t transfer completed: nok", $time);`
286	2	simons
287	9	simons	`i_spi_slave.rx_negedge = 1'b1;`
288	2	simons	`i_spi_slave.tx_negedge = 1'b0;`
289	9	simons	`i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);`
290	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h3220);`
291			`i_wb_master.wb_write(0, SPI_CTRL, 32'h3320);`
292	2	simons
293	9	simons	`$display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);`
294	2	simons
295			`while (!int)`
296			`@(posedge clk);`
297
298	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
299	25	simons	`result = result + q;`
300	2	simons
301			`@(posedge clk);`
302	9	simons	`if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)`
303			`$display("status: %t transfer completed: ok", $time);`
304	2	simons	`else`
305	9	simons	`$display("status: %t transfer completed: nok", $time);`
306	2	simons
307	9	simons	`i_spi_slave.rx_negedge = 1'b1;`
308			`i_spi_slave.tx_negedge = 1'b0;`
309			`i_wb_master.wb_write(0, SPI_TX_0, 32'h1);`
310	25	simons	`i_wb_master.wb_write(0, SPI_CTRL, 32'h3201);`
311			`i_wb_master.wb_write(0, SPI_CTRL, 32'h3301);`
312	7	simons
313	9	simons	`$display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);`
314	7	simons
315			`while (!int)`
316			`@(posedge clk);`
317
318	9	simons	`i_wb_master.wb_read(1, SPI_RX_0, q);`
319	25	simons	`result = result + q;`
320	7	simons
321			`@(posedge clk);`
322	9	simons	`if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)`
323			`$display("status: %t transfer completed: ok", $time);`
324	7	simons	`else`
325	9	simons	`$display("status: %t transfer completed: nok", $time);`
326	7	simons
327	2	simons	`$display("\n\nstatus: %t Testbench done", $time);`
328
329			`#25000; // wait 25us`
330
331	25	simons	`$display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead);`
332			`$display("exit (%h)", result ^ 32'h2e8b36ab);`
333
334	2	simons	`$stop;`
335			`end`
336
337			`endmodule`
338
339

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[/] [spi/] [trunk/] [bench/] [verilog/] [tb_spi_top.v] - Blame information for rev 29