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[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_defines.v] - Blame information for rev 13

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_define.v                                                ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//
// Number of bits used for devider register. If used in system with
// low frequency of system clock this can be reduced.
// Default is 16.
//
//`define SPI_DIVIDER_LEN_8
`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_32
 
//
// Maximum nuber of bits that can be send/received at once. 
//
`define SPI_MAX_CHAR_128
//`define SPI_MAX_CHAR_64
//`define SPI_MAX_CHAR_32
//`define SPI_MAX_CHAR_16
//`define SPI_MAX_CHAR_8
 
//
// Number of device select signals.
//
`define SPI_SS_NB_8
//`define SPI_SS_NB_16
//`define SPI_SS_NB_32
 
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
`define SPI_OFS_BITS              4:2
 
//
// Register offset
//
`define SPI_RX_0                0
`define SPI_RX_1                1
`define SPI_RX_2                2
`define SPI_RX_3                3
`define SPI_TX_0                0
`define SPI_TX_1                1
`define SPI_TX_2                2
`define SPI_TX_3                3
`define SPI_CTRL                4
`define SPI_DEVIDE              5
`define SPI_SS                  6
 
//
// Number of bits in ctrl register
//
`define SPI_CTRL_BIT_NB         13
 
//
// Control register bit position
//
`define SPI_CTRL_ASS            12
`define SPI_CTRL_IE             11
`define SPI_CTRL_LSB            10
`define SPI_CTRL_CHAR_LEN       9:3
`define SPI_CTRL_TX_NEGEDGE     2
`define SPI_CTRL_RX_NEGEDGE     1
`define SPI_CTRL_GO             0
 
 
`ifdef SPI_DIVIDER_LEN_8
  `define SPI_DIVIDER_LEN       8
`endif
`ifdef SPI_DIVIDER_LEN_16
  `define SPI_DIVIDER_LEN       16
`endif
`ifdef SPI_DIVIDER_LEN_32
  `define SPI_DIVIDER_LEN       32
`endif
 
`ifdef SPI_MAX_CHAR_128
  `define SPI_MAX_CHAR          128
  `define SPI_CHAR_LEN_BITS     7
`endif
`ifdef SPI_MAX_CHAR_64
  `define SPI_MAX_CHAR          64
  `define SPI_CHAR_LEN_BITS     6
`endif
`ifdef SPI_MAX_CHAR_32
  `define SPI_MAX_CHAR          32
  `define SPI_CHAR_LEN_BITS     5
`endif
`ifdef SPI_MAX_CHAR_16
  `define SPI_MAX_CHAR          16
  `define SPI_CHAR_LEN_BITS     4
`endif
`ifdef SPI_MAX_CHAR_8
  `define SPI_MAX_CHAR          8
  `define SPI_CHAR_LEN_BITS     3
`endif
 
`ifdef SPI_SS_NB_8
  `define SPI_SS_NB             8
`endif
`ifdef SPI_SS_NB_16
  `define SPI_SS_NB             16
`endif
`ifdef SPI_SS_NB_32
  `define SPI_SS_NB             32
`endif
 
 

Line No.	Rev	Author	Line
1	2	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_define.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			`//`
42			`// Number of bits used for devider register. If used in system with`
43			`// low frequency of system clock this can be reduced.`
44			`// Default is 16.`
45			`//`
46	13	simons	//`define SPI_DIVIDER_LEN_8
47			`define SPI_DIVIDER_LEN_16
48			//`define SPI_DIVIDER_LEN_32
49	2	simons
50			`//`
51	13	simons	`// Maximum nuber of bits that can be send/received at once.`
52	2	simons	`//`
53	13	simons	`define SPI_MAX_CHAR_128
54			//`define SPI_MAX_CHAR_64
55			//`define SPI_MAX_CHAR_32
56			//`define SPI_MAX_CHAR_16
57			//`define SPI_MAX_CHAR_8
58	2	simons
59			`//`
60			`// Number of device select signals.`
61			`//`
62	13	simons	`define SPI_SS_NB_8
63			//`define SPI_SS_NB_16
64			//`define SPI_SS_NB_32
65
66	2	simons	`//`
67			`// Bits of WISHBONE address used for partial decoding of SPI registers.`
68			`//`
69	7	simons	`define SPI_OFS_BITS 4:2
70	2	simons
71			`//`
72			`// Register offset`
73			`//`
74	9	simons	`define SPI_RX_0 0
75			`define SPI_RX_1 1
76			`define SPI_RX_2 2
77			`define SPI_RX_3 3
78			`define SPI_TX_0 0
79			`define SPI_TX_1 1
80			`define SPI_TX_2 2
81			`define SPI_TX_3 3
82			`define SPI_CTRL 4
83			`define SPI_DEVIDE 5
84			`define SPI_SS 6
85	2	simons
86			`//`
87			`// Number of bits in ctrl register`
88			`//`
89	9	simons	`define SPI_CTRL_BIT_NB 13
90	2	simons
91			`//`
92			`// Control register bit position`
93			`//`
94	9	simons	`define SPI_CTRL_ASS 12
95			`define SPI_CTRL_IE 11
96			`define SPI_CTRL_LSB 10
97			`define SPI_CTRL_CHAR_LEN 9:3
98	2	simons	`define SPI_CTRL_TX_NEGEDGE 2
99			`define SPI_CTRL_RX_NEGEDGE 1
100			`define SPI_CTRL_GO 0
101
102
103	13	simons	`ifdef SPI_DIVIDER_LEN_8
104			`define SPI_DIVIDER_LEN 8
105			`endif
106			`ifdef SPI_DIVIDER_LEN_16
107			`define SPI_DIVIDER_LEN 16
108			`endif
109			`ifdef SPI_DIVIDER_LEN_32
110			`define SPI_DIVIDER_LEN 32
111			`endif
112
113			`ifdef SPI_MAX_CHAR_128
114			`define SPI_MAX_CHAR 128
115			`define SPI_CHAR_LEN_BITS 7
116			`endif
117			`ifdef SPI_MAX_CHAR_64
118			`define SPI_MAX_CHAR 64
119			`define SPI_CHAR_LEN_BITS 6
120			`endif
121			`ifdef SPI_MAX_CHAR_32
122			`define SPI_MAX_CHAR 32
123			`define SPI_CHAR_LEN_BITS 5
124			`endif
125			`ifdef SPI_MAX_CHAR_16
126			`define SPI_MAX_CHAR 16
127			`define SPI_CHAR_LEN_BITS 4
128			`endif
129			`ifdef SPI_MAX_CHAR_8
130			`define SPI_MAX_CHAR 8
131			`define SPI_CHAR_LEN_BITS 3
132			`endif
133
134			`ifdef SPI_SS_NB_8
135			`define SPI_SS_NB 8
136			`endif
137			`ifdef SPI_SS_NB_16
138			`define SPI_SS_NB 16
139			`endif
140			`ifdef SPI_SS_NB_32
141			`define SPI_SS_NB 32
142			`endif
143
144

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[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_defines.v] - Blame information for rev 13