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[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_defines.v] - Blame information for rev 9

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_define.v                                                ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
//
// Number of bits used for devider register. If used in system with
// low frequency of system clock this can be reduced.
// Default is 16.
//
`define SPI_DIVIDER_BIT_NB      16
 
//
// Maximum nuber of bits that can be send/received at once. Alloved values are
// 128, 64, 32, 16 and 8. SPI_CHAR_LEN_BITS must be also set to 7, 6, 5, 4 or 3 respectively.
// Default is 128.
// If SPI_MAX_CHAR is 64 or 128, SPI_MAX_CHAR_64 or SPI_MAX_CHAR_128 must be defined, 
// otherwise comment it out.
//
`define SPI_MAX_CHAR_128        1
//`define SPI_MAX_CHAR_64         1
`define SPI_MAX_CHAR            128
`define SPI_CHAR_LEN_BITS       7
 
//
// Number of device select signals.
//
`define SPI_SS_NB               8
//
// Bits of WISHBONE address used for partial decoding of SPI registers.
//
`define SPI_OFS_BITS              4:2
 
//
// Register offset
//
`define SPI_RX_0                0
`define SPI_RX_1                1
`define SPI_RX_2                2
`define SPI_RX_3                3
`define SPI_TX_0                0
`define SPI_TX_1                1
`define SPI_TX_2                2
`define SPI_TX_3                3
`define SPI_CTRL                4
`define SPI_DEVIDE              5
`define SPI_SS                  6
 
//
// Number of bits in ctrl register
//
`define SPI_CTRL_BIT_NB         13
 
//
// Control register bit position
//
`define SPI_CTRL_ASS            12
`define SPI_CTRL_IE             11
`define SPI_CTRL_LSB            10
`define SPI_CTRL_CHAR_LEN       9:3
`define SPI_CTRL_TX_NEGEDGE     2
`define SPI_CTRL_RX_NEGEDGE     1
`define SPI_CTRL_GO             0
 
 

Line No.	Rev	Author	Line
1	2	simons	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_define.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40
41			`//`
42			`// Number of bits used for devider register. If used in system with`
43			`// low frequency of system clock this can be reduced.`
44			`// Default is 16.`
45			`//`
46			`define SPI_DIVIDER_BIT_NB 16
47
48			`//`
49			`// Maximum nuber of bits that can be send/received at once. Alloved values are`
50	9	simons	`// 128, 64, 32, 16 and 8. SPI_CHAR_LEN_BITS must be also set to 7, 6, 5, 4 or 3 respectively.`
51			`// Default is 128.`
52			`// If SPI_MAX_CHAR is 64 or 128, SPI_MAX_CHAR_64 or SPI_MAX_CHAR_128 must be defined,`
53			`// otherwise comment it out.`
54	2	simons	`//`
55	9	simons	`define SPI_MAX_CHAR_128 1
56			//`define SPI_MAX_CHAR_64 1
57			`define SPI_MAX_CHAR 128
58			`define SPI_CHAR_LEN_BITS 7
59	2	simons
60			`//`
61			`// Number of device select signals.`
62			`//`
63			`define SPI_SS_NB 8
64			`//`
65			`// Bits of WISHBONE address used for partial decoding of SPI registers.`
66			`//`
67	7	simons	`define SPI_OFS_BITS 4:2
68	2	simons
69			`//`
70			`// Register offset`
71			`//`
72	9	simons	`define SPI_RX_0 0
73			`define SPI_RX_1 1
74			`define SPI_RX_2 2
75			`define SPI_RX_3 3
76			`define SPI_TX_0 0
77			`define SPI_TX_1 1
78			`define SPI_TX_2 2
79			`define SPI_TX_3 3
80			`define SPI_CTRL 4
81			`define SPI_DEVIDE 5
82			`define SPI_SS 6
83	2	simons
84			`//`
85			`// Number of bits in ctrl register`
86			`//`
87	9	simons	`define SPI_CTRL_BIT_NB 13
88	2	simons
89			`//`
90			`// Control register bit position`
91			`//`
92	9	simons	`define SPI_CTRL_ASS 12
93			`define SPI_CTRL_IE 11
94			`define SPI_CTRL_LSB 10
95			`define SPI_CTRL_CHAR_LEN 9:3
96	2	simons	`define SPI_CTRL_TX_NEGEDGE 2
97			`define SPI_CTRL_RX_NEGEDGE 1
98			`define SPI_CTRL_GO 0
99
100

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[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_defines.v] - Blame information for rev 9