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URL https://opencores.org/ocsvn/spi2ram/spi2ram/trunk

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[/] [spi2ram/] [trunk/] [spi2ram.v] - Blame information for rev 2

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1 2 longquan 
module spi2ram
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(
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    //spi interface
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    input spi_sck,
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    input spi_cs,
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    input spi_mosi,
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    output  spi_miso,
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    //ram interface
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    output [15:0] sAddress ,
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    output sCSn,
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    output sOEn,
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    output sWRn,
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    output sDqDir,
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    output [7:0] sDqOut,
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    input [7:0] sDqIn
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);
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    reg [7:0] rINBUF;
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    reg [7:0] rOUTBUF;
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    assign spi_miso = rOUTBUF[7];
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    reg [5:0] rCnt;
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    reg  rCntOV;
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    wire sCnt8;
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    assign sCnt8 = (~|(rCnt[2:0])) & ((|rCnt[5:3]) | rCntOV);
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    //assign sCnt8 = (~|(rCnt[2:0])) & ((|rCnt[5:3]) );
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    reg [7:0] rCmd;
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    reg [7:0] rState;
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    reg [15:0] rAddress;
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    reg rReadFlag1, rReadFlag2;
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    assign sAddress = rReadFlag1 ? {rAddress[15:8], rINBUF} : rAddress;
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    wire sRamOE;
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    assign sRamOE = sCnt8 & (rReadFlag1 | rReadFlag2);
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    reg rWriteFlag1;
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    wire sRamWR;
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    assign sRamWR = sCnt8 & spi_sck & rWriteFlag1;
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    //reg [7:0] rRamWrBuf;
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    //assign sDqOut = sRamWR?rINBUF:8'h00;
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    assign sDqOut =  rINBUF;
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    reg rCmdGotFlag;
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    assign sCSn = sOEn & sWRn;
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    assign sOEn = ~sRamOE;
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    assign sWRn = ~sRamWR;
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    assign sDqDir = sRamWR;
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    always@(posedge spi_sck , posedge spi_cs )begin
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        if(spi_cs)begin
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            rINBUF <= 'b0;
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            rCnt <= 'b0;
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        end
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        else
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        begin
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            rINBUF <= {rINBUF[6:0], spi_mosi};
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            rCnt <= rCnt + 1'b1;
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        end
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    end
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    always@( negedge spi_sck , posedge spi_cs ) begin
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        if(spi_cs)begin
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            rWriteFlag1 <= 'b0;
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            rReadFlag1 <= 'b0;
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            rReadFlag2 <= 'b0;
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            rAddress <= 'b0;
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            rCmdGotFlag <= 0;
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            rCmd  <= 0;
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                                rCntOV <= 1'b0;
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        end
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        else
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        if(sCnt8)begin
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            if(!rCmdGotFlag)begin
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                rCmdGotFlag <= 1'b1;
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                                         rCntOV <= 1'b1;
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                rCmd <= rINBUF;
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                if(rINBUF == 8'h05) rOUTBUF <= rState;
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                if(rINBUF == 8'h04) rState[1] <= 1'b0;
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                if(rINBUF == 8'h06) rState[1] <= 1'b1;
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                if(rINBUF == 8'h9f) rOUTBUF <= 8'h20;
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            end
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            else begin
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                case(rCmd[3:0])
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                4'h1:begin
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                    if( rCnt[5:3] == 3'b010 ) rState <= rINBUF;
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                    end
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                4'h2:begin
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                    if( rWriteFlag1 == 'b0 )begin
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                        case( rCnt[5:3])
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                        3'b010: begin
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                            rAddress[15:8] <= rINBUF;
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                        end
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                        3'b011: begin
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                            rAddress[15:0] <= {rAddress[15:8], rINBUF};
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                            rWriteFlag1 <= 1'b1;
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                        end
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                        endcase
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                    end
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                    else begin
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                        //rRamWrBuf <= rINBUF;
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                        rAddress <= rAddress + 1'b1;
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                    end
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                    end
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                4'h3:begin
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                    if( rReadFlag2 == 'b0 )begin
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                        case( rCnt[5:3])
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                        3'b010: begin
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                                                                        rAddress[15:8] <= rINBUF;
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                                                                        rOUTBUF <= 8'h00;
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                                                                        rReadFlag1 <= 'b1;
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                                                                        end
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                        3'b011: begin
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                                                                        rAddress[15:0] <= {rAddress[15:8], rINBUF} + 1'b1;
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                                                                        rOUTBUF <= sDqIn;
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                                                                        rReadFlag2 <= 'b1;
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                                                                        rReadFlag1<= 'b0;
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                        end
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                        endcase
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                    end
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                    else begin
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                        rOUTBUF <= sDqIn;
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                        rAddress <= rAddress + 1'b1;
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                    end
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                    end
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                4'h4:begin
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                    end
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                4'h5:begin
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                                                                rOUTBUF <= rState;
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                    end
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                4'h6:begin
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                    end
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                4'hf:begin
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                        case( rCnt[5:3])
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                        3'b010: begin
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                            rOUTBUF <= 8'h11;
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                        end
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                        3'b011: begin
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                            rOUTBUF <= 8'h22;
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                        end
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                        endcase
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                    end
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                 default:begin
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                    end
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                endcase
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            end
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        end
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        else begin
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            rOUTBUF <= {rOUTBUF[6:0],1'b0};
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        end
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    end
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endmodule

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