OpenCores
URL https://opencores.org/ocsvn/spi2ram/spi2ram/trunk

Subversion Repositories spi2ram

[/] [spi2ram/] [trunk/] [spiflashtb.v] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 longquan 
module top_module ();
2 
        reg clk=0;
3 
 
4 
    reg spi_sck,spi_cs,spi_mosi,spi_clk ;
5 
 
6 
    wire spi_miso;
7 
    wire[16:0] nvram_addr;
8 
    wire nvram_en;
9 
    wire nvram_g;
10 
    wire nvram_w;
11 
 
12 
    reg sys_clk;
13 
    reg sys_rstn;
14 
 
15 
    parameter           clockperiod = 10;
16 
    parameter           clockperiod1 = 8;
17 
 
18 
 
19 
 
20 
    initial
21 
    begin
22 
        sys_rstn = 0;
23 
        sys_clk = 0;
24 
        #15
25 
        sys_rstn = 1;
26 
    end
27 
 
28 
    initial
29 
    begin
30 
        spi_sck = 1'b0;
31 
        //repeat(1000) spi_sck = #(clockperiod/2)~spi_sck;
32 
    end
33 
 
34 
 
35 
 
36 
        initial `probe_start;   // Start the timing diagram
37 
 
38 
        // A testbench
39 
 
40 
        initial begin
41 
     #80;
42 
         spi_cs = 1'b0;
43 
         #20;spi_cs = 1'b1;
44 
        #20;
45 
        spi_cs = 1'b0;
46 
          #20;
47 
        spi_cs = 1'b1;
48 
        #20;
49 
        spi_cs = 1'b0;
50 
        datasend(8'h02);
51 
        datasend(8'h10);
52 
        datasend(8'h33);
53 
        datasend(8'haa);
54 
        datasend(8'haa);
55 
        datasend(8'haa);
56 
         spi_cs = 1'b1;
57 
         #20;
58 
         spi_cs = 1'b0;
59 
         #20;
60 
         spi_cs = 1'b1;
61 
 
62 
         $finish;            // Quit the simulation
63 
        end
64 
 
65 
 
66 
 
67 
    task datasend(input [7:0] senddata);
68 
        begin
69 
            #5;
70 
        spi_sck = 1'b0;
71 
        spi_mosi = senddata[7];
72 
        #5;
73 
            spi_sck = 1'b1;
74 
        #5;
75 
            spi_sck = 1'b0;
76 
            spi_mosi = senddata[6];
77 
        #5;
78 
            spi_sck = 1'b1;
79 
        #5;
80 
            spi_sck = 1'b0;
81 
            spi_mosi = senddata[5];
82 
        #5;
83 
        spi_sck = 1'b1;
84 
        #5;
85 
        spi_sck = 1'b0;
86 
            spi_mosi = senddata[4];
87 
        #5;
88 
        spi_sck = 1'b1;
89 
        #5;
90 
        spi_sck = 1'b0;
91 
            spi_mosi = senddata[3];
92 
        #5;
93 
        spi_sck = 1'b1;
94 
        #5;
95 
        spi_sck = 1'b0;
96 
            spi_mosi = senddata[2];
97 
        #5;
98 
        spi_sck = 1'b1;
99 
        #5;
100 
        spi_sck = 1'b0;
101 
            spi_mosi = senddata[1];
102 
        #5;
103 
        spi_sck = 1'b1;
104 
        #5;
105 
        spi_sck = 1'b0;
106 
            spi_mosi = senddata[0];
107 
        #5;
108 
        spi_sck = 1'b1;
109 
        #5;
110 
        spi_sck = 1'b0;
111 
        #5;
112 
 
113 
        end
114 
    endtask
115 
    spi_slave_nvram spi_slave_nvram_sim (
116 
    .sys_rstn(sys_rstn),
117 
    .spi_sck(spi_sck),
118 
    .spi_cs(spi_cs),
119 
    .spi_mosi(spi_mosi),
120 
    .spi_miso(spi_miso)
121 
 
122 
    );
123 
 
124 
 
125 
    `probe(spi_sck);        // Probe signal "clk"
126 
    `probe(spi_mosi);        // Probe signal "clk"
127 
        `probe(sys_rstn);        // Probe signal "clk"
128 
        `probe(spi_cs);        // Probe signal "clk"
129 
    `probe(spi_miso);        // Probe signal "clk"
130 
 
131 
endmodule
132 
 
133 
module spi_slave_nvram
134 
(
135 
input sys_clk,
136 
input sys_rstn,
137 
//spi interface
138 
input spi_sck,
139 
input spi_cs,
140 
input spi_mosi,
141 
output  spi_miso,
142 
//nvram interface
143 
    output reg   [7:0] nvram_dq ,
144 
    output reg   [7:0] nvram_dq1,
145 
    output reg   [7:0] nvram_dq2
146 
 
147 
);
148 
 
149 
    reg [7:0] rINBUF;
150 
    reg [7:0] rOUTBUF;
151 
    assign spi_miso = rOUTBUF[7];
152 
    reg rCStart[1:0];
153 
    reg [5:0] rCnt;
154 
    wire sCnt8;
155 
    assign sCnt8 = (~|(rCnt[2:0])) & (|rCnt[5:3]);
156 
 
157 
    reg rFlagData;
158 
 
159 
 
160 
    always@(posedge spi_sck or posedge spi_cs )begin
161 
        if(spi_cs)begin
162 
            rINBUF <= 'b0;
163 
            rCnt <= 'b0;
164 
        end
165 
        else
166 
        begin
167 
               rINBUF <= {rINBUF[6:0], spi_mosi};
168 
               rCnt <= rCnt + 1'b1;
169 
        end
170 
    end
171 
 
172 
    reg [7:0] rCmd;
173 
    always@( negedge spi_sck) begin
174 
        if(sCnt8)begin
175 
            case( rCnt[4:3])
176 
                2'b00: begin nvram_dq <= rINBUF;  rOUTBUF <= 8'hf1; end
177 
                2'b01: begin nvram_dq1 <= rINBUF; rOUTBUF <= 8'haa; end
178 
                2'b10: begin nvram_dq2 <= rINBUF; rOUTBUF <= 8'h80; end
179 
                2'b11: begin nvram_dq <= rINBUF;  rOUTBUF <= 8'h22; end
180 
            endcase
181 
 
182 
        end
183 
        else begin
184 
            rOUTBUF <= {rOUTBUF[6:0],1'b0};
185 
        end
186 
    end
187 
 
188 
    `probe(rCnt);
189 
 
190 
    `probe(spi_sck);
191 
    `probe(rINBUF);
192 
    `probe(rOUTBUF);
193 
    `probe(sCnt8);
194 
    `probe(nvram_dq);
195 
    `probe(nvram_dq1);
196 
    `probe(nvram_dq2);
197 
 
198 
 
199 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.