Subversion Repositories spi_boot

README for the spi_boot core

============================

Version: $Date: 2005-02-18 06:54:36 $

Description

-----------

The SD/MMC Bootloader is a CPLD design that manages configuration and

bootstrapping of FPGAs. It is able to retrieve the required data from

SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA

configuration process. SD cards as well as MMCs are operated in SPI mode which

is part of both standards thus eliminating the need for dedicated

implementations. The SD/MMC Bootloader fits both. Beyond configuration, this

core supports a bootstrapping strategy where multiple images are stored on one

single memory card.

For example consider a system completely based on SRAM. The bootloader

provides an initial configuration data from the first image to the FPGA. This

image contains a design which pulls the next image from the memory card and

transfers this data to SRAM. In the third step the final FPGA design is loaded

from the third image.

Features

--------

* Configuration mode: configurates SRAM based FPGAs via slave serial mode

  (Xilinx and Altera)

* Data mode: provides stored data over a simple synchronous serial interface

* Broad compatability using SPI mode

    + SecureDigital cards using dedicated initialization command

    + MultiMediaCards (see below)

* Operation triggerd by power-up or card insertion

Compatability

-------------

These cards have been tested with the SD/MMC Bootloader:

  * SanDisk 128 MB SD

  * SanDisk 64 MB MMC

  * Panasonic 32 MB SD

Some MMC might fail with this core as not all cards support CMD18

(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific

model. In case your MMC does not implement CMD18 you might want to have a look

at the FPGA MMC-Card Config project.

Verification

------------

The spi_boot core comes with a simple testbench that simulates an SD/MMC

card. All four implementations of the core are verified there in parallel

while transferring the data for several sets.

You should normally not need to run the testbench. But in case you modified

the VHDL code the testbench gives some hints if the design has been broken.

Directory Structure

-------------------

The core's directory structure follows the proposal of OpenCores.org.

spi_boot

 |

 \--+-- rtl

    |    |

    |    \-- vhdl           : VHDL code containing the RTL description

    |                         of the core.

    |

    +-- bench

    |    |

    |    \-- vhdl           : VHDL testbench code.

    |

    \-- sim

         |

         \-- rtl_sim        : Directory for running simulations.

Compiling the VHDL Code

-----------------------

VHDL compilation and simulation tasks take place inside in sim/rtl_sim

directory. The project setup supports only the GHDL simulator (see

http://ghdl.free.fr).

To compile the code simply type at the shell

$ make

This should result in a file called tb_behav_c0 which can be executed as any

other executable.

The basic simple sequence list can be found in COMPILE_LIST. This can be

useful to quickly set up the analyze stage of any compiler or

synthesizer. Especially when synthesizing the code, you want to skip the VHDL

configurations in *-c.vhd and everything below the bench/ directory.

References

----------

  * SanDisk SD Card Product Manual

    http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf

  * SanDisk MMC Product Manual

    http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf

  * Toshiba SD Card Specification

    http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf

  * FPGA MMC-Card Config project

    http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview