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[/] [spi_boot/] [trunk/] [bench/] [vhdl/] [tb_elem.vhd] - Blame information for rev 16

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1 4 arniml
-------------------------------------------------------------------------------
2
--
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-- SD/MMC Bootloader
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-- Generic testbench element for a specific feature set
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--
6 16 arniml
-- $Id: tb_elem.vhd,v 1.4 2005-02-17 18:59:23 arniml Exp $
7 4 arniml
--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved, see COPYING.
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
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--
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-------------------------------------------------------------------------------
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47
library ieee;
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use ieee.std_logic_1164.all;
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entity tb_elem is
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  generic (
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    chip_type_g   : string := "none";
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    has_sd_card_g : integer := 1
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  );
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  port (
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    clk_i   : in  std_logic;
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    reset_i : in  std_logic;
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    eos_o   : out boolean
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  );
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end tb_elem;
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library ieee;
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use ieee.numeric_std.all;
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library std;
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use std.textio.all;
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use work.spi_boot_pack.all;
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use work.tb_pack.all;
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architecture behav of tb_elem is
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  component chip
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    port (
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      clk_i          : in  std_logic;
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      reset_i        : in  std_logic;
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      spi_clk_o      : out std_logic;
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      spi_cs_n_o     : out std_logic;
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      spi_data_in_i  : in  std_logic;
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      spi_data_out_o : out std_logic;
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      start_i        : in  std_logic;
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      mode_i         : in  std_logic;
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      config_n_o     : out std_logic;
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      cfg_init_n_i   : in  std_logic;
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      cfg_done_i     : in  std_logic;
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      dat_done_i     : in  std_logic;
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      cfg_clk_o      : out std_logic;
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      cfg_dat_o      : out std_logic
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    );
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  end component;
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95
  component card
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    generic (
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      card_type_g  : string := "none";
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      is_sd_card_g : integer := 1
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    );
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    port (
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      spi_clk_i  : in  std_logic;
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      spi_cs_n_i : in  std_logic;
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      spi_data_i : in  std_logic;
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      spi_data_o : out std_logic
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    );
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  end component;
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  -- SPI interface signals
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  signal spi_clk_s            : std_logic;
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  signal spi_data_to_card_s   : std_logic;
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  signal spi_data_from_card_s : std_logic;
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  signal spi_cs_n_s           : std_logic;
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  -- config related signals
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  signal start_s      : std_logic;
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  signal mode_s       : std_logic;
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  signal config_n_s   : std_logic;
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  signal cfg_init_n_s : std_logic;
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  signal cfg_done_s   : std_logic;
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  signal dat_done_s   : std_logic;
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  signal cfg_clk_s    : std_logic;
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  signal cfg_dat_s    : std_logic;
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  signal data_s       : unsigned( 7 downto 0);
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begin
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127 15 arniml
  -- weak pull-ups
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  spi_clk_s          <= 'H';
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  spi_cs_n_s         <= 'H';
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  spi_data_to_card_s <= 'H';
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132 4 arniml
  -----------------------------------------------------------------------------
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  -- DUT
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  -----------------------------------------------------------------------------
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  dut_b : chip
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    port map (
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      clk_i          => clk_i,
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      reset_i        => reset_i,
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      spi_clk_o      => spi_clk_s,
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      spi_cs_n_o     => spi_cs_n_s,
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      spi_data_in_i  => spi_data_from_card_s,
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      spi_data_out_o => spi_data_to_card_s,
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      start_i        => start_s,
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      mode_i         => mode_s,
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      config_n_o     => config_n_s,
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      cfg_init_n_i   => cfg_init_n_s,
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      cfg_done_i     => cfg_done_s,
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      dat_done_i     => dat_done_s,
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      cfg_clk_o      => cfg_clk_s,
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      cfg_dat_o      => cfg_dat_s
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    );
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  card_b : card
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    generic map (
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      card_type_g  => chip_type_g,
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      is_sd_card_g => has_sd_card_g
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    )
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    port map (
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      spi_clk_i  => spi_clk_s,
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      spi_cs_n_i => spi_cs_n_s,
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      spi_data_i => spi_data_to_card_s,
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      spi_data_o => spi_data_from_card_s
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    );
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166
  -----------------------------------------------------------------------------
167
  -- DUT Stimuli
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  --
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  stim: process
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171
    procedure rise_cfg_clk(num : integer) is
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    begin
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      for i in 1 to num loop
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        wait until cfg_clk_s'event and cfg_clk_s = '1';
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      end loop;
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    end rise_cfg_clk;
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--     procedure fall_cfg_clk(num : integer) is
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--     begin
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--       for i in 1 to num loop
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--         wait until cfg_clk_s'event and cfg_clk_s = '0';
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--       end loop;
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--     end fall_cfg_clk;
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    procedure rise_clk(num : integer) is
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    begin
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      for i in 1 to num loop
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        wait until clk_i'event and clk_i = '1';
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      end loop;
190
    end rise_clk;
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    procedure read_check_byte(ref : unsigned(7 downto 0)) is
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      variable byte_v : unsigned(7 downto 0);
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      variable dump_line : line;
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    begin
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      for bit in 7 downto 0 loop
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        rise_cfg_clk(1);
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        byte_v(bit) := cfg_dat_s;
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      end loop;
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      data_s <= byte_v;
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      if byte_v /= ref then
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        write(dump_line, chip_type_g);
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        write(dump_line, string'(" at "));
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        write(dump_line, now);
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        write(dump_line, string'(": read_check_byte failed "));
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        write(dump_line, to_integer(byte_v));
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        write(dump_line, string'(" "));
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        write(dump_line, to_integer(ref));
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        writeline(output, dump_line);
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      end if;
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    end read_check_byte;
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214
    variable dump_line : line;
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    variable addr_v    : unsigned(31 downto 0);
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    variable temp_v    : unsigned( 7 downto 0);
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218
  begin
219
    -- default assignments
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    -- these defaults show the required pull resistors
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    -- except start_i as this must be pulled high for automatic start
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    start_s      <= '0';
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    mode_s       <= '1';
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    cfg_init_n_s <= '1';
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    cfg_done_s   <= '0';
226 7 arniml
    dat_done_s   <= '1';
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    data_s       <= (others => '1');
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    addr_v       := (others => '0');
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    eos_o        <= false;
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    wait for 100 us;
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    -- signal start
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    start_s <= '1';
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    wait until config_n_s = '0';
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    -- run through configuration sequence
236
    rise_clk(1);
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    cfg_init_n_s <= '0';
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    rise_clk(3);
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    cfg_init_n_s <= '1';
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241 16 arniml
    -- and receive 32 bytes from image 0
242 4 arniml
    for i in 1 to 32 loop
243
      temp_v := addr_v(0) & calc_crc(addr_v);
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      read_check_byte(temp_v);
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      addr_v := addr_v + 1;
246
    end loop;
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    start_s    <= '0';
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    cfg_done_s <= '1';
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    rise_clk(10);
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    -- request next image
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    mode_s  <= '0';
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    start_s <= '1';
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    addr_v  := (others => '0');
256 16 arniml
    addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
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    dat_done_s <= '0';
258 4 arniml
 
259 16 arniml
    -- receive another 32 bytes from image 1
260 4 arniml
    for i in 1 to 32 loop
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      temp_v := addr_v(0) & calc_crc(addr_v);
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      read_check_byte(temp_v);
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      addr_v := addr_v + 1;
264
    end loop;
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    start_s    <= '0';
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    dat_done_s <= '1';
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269
    rise_clk(10);
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271 16 arniml
    -- request next image
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    mode_s  <= '1';
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    start_s <= '1';
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    addr_v  := (others => '0');
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    addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
276 4 arniml
 
277
    wait until config_n_s = '0';
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    -- run through configuration sequence
279
    rise_clk(1);
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    cfg_done_s   <= '0';
281
    cfg_init_n_s <= '0';
282
    rise_clk(3);
283
    cfg_init_n_s <= '1';
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285 16 arniml
    -- receive another 32 bytes from image 2
286 4 arniml
    for i in 1 to 32 loop
287
      temp_v := addr_v(0) & calc_crc(addr_v);
288
      read_check_byte(temp_v);
289
      addr_v := addr_v + 1;
290
    end loop;
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    start_s    <= '0';
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    cfg_done_s <= '1';
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294
    -- give dut a chance to stop current transfer
295
    wait until spi_cs_n_s = '1';
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    rise_clk(10);
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    eos_o <= true;
298
    wait;
299
  end process stim;
300
  --
301
  -----------------------------------------------------------------------------
302
 
303
end behav;
304
 
305
 
306
-------------------------------------------------------------------------------
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-- File History:
308
--
309
-- $Log: not supported by cvs2svn $
310 16 arniml
-- Revision 1.3  2005/02/16 19:34:56  arniml
311
-- add weak pull-ups for SPI lines
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--
313 15 arniml
-- Revision 1.2  2005/02/13 17:14:03  arniml
314
-- change dat_done handling
315
--
316 7 arniml
-- Revision 1.1  2005/02/08 21:09:20  arniml
317
-- initial check-in
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--
319 4 arniml
-------------------------------------------------------------------------------

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