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[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [adc.v] - Blame information for rev 2

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module adc(sdo,spi_clk,clk,rst,conv);
        parameter WIDTH=14; //multiple of two
        parameter PATTERN = {WIDTH/2{2'b10}};
        parameter COUNTMAX = 34;
 
        input rst, conv, spi_clk, clk;
        output sdo;
 
        reg [WIDTH-1:0] mem;
        reg sdo;
 
        reg flag;
        reg [6:0] count;
 
        integer N;
 
        initial
        begin
                mem = PATTERN;
        end
 
/*      always@ (posedge conv or posedge rst)
        begin
                if(rst)
                        flag <= 0;
                else
                        flag <= 1;
        end*/
 
        always@ (posedge clk or posedge rst)
        begin
                if(rst)
                        flag <= 0;
                else if (conv)
                        flag <= 1;
                else if (count == COUNTMAX)
                begin
                        count <= 'b0;
                        flag <= 0;
                        mem = ~mem;
                end
        end
 
        always @(negedge spi_clk or posedge rst)
        begin
                if (rst)
                        count <= 0;
                else if(flag & !rst)
                        if(count==COUNTMAX)
                                count <= 'b0;
                        else
                                count <= count+1;
        end
 
        always@(count)
        begin
        case(count)
 
                1 : sdo <= 'bZ;
                2 : sdo <= 'bZ;
                3 : sdo <= mem[13];
                4 : sdo <= mem[12];
                5 : sdo <= mem[11];
                6 : sdo <= mem[10];
                7 : sdo <= mem[9];
                8 : sdo <= mem[8];
                9 : sdo <= mem[7];
                10 : sdo <= mem[6];
                11 : sdo <= mem[5];
                12 : sdo <= mem[4];
                13 : sdo <= mem[3];
                14 : sdo <= mem[2];
                15 : sdo <= mem[1];
                16 : sdo <= mem[0];
                17 : sdo <= 'bZ;
                18 : sdo <= 'bZ;
                19 : sdo <= mem[13];
                20 : sdo <= mem[12];
                21 : sdo <= mem[11];
                22 : sdo <= mem[10];
                23 : sdo <= mem[9];
                24 : sdo <= mem[8];
                25 : sdo <= mem[7];
                26 : sdo <= mem[6];
                27 : sdo <= mem[5];
                28 : sdo <= mem[4];
                29 : sdo <= mem[3];
                30 : sdo <= mem[2];
                31 : sdo <= mem[1];
                32 : sdo <= mem[0];
                33 : sdo <= 'bZ;
                34 : sdo <= 'bZ;
                default: sdo <= 'bZ;
        endcase
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	williamgib	`module adc(sdo,spi_clk,clk,rst,conv);`
2			`parameter WIDTH=14; //multiple of two`
3			`parameter PATTERN = {WIDTH/2{2'b10}};`
4			`parameter COUNTMAX = 34;`
5
6			`input rst, conv, spi_clk, clk;`
7			`output sdo;`
8
9			`reg [WIDTH-1:0] mem;`
10			`reg sdo;`
11
12			`reg flag;`
13			`reg [6:0] count;`
14
15			`integer N;`
16
17			`initial`
18			`begin`
19			`mem = PATTERN;`
20			`end`
21
22			`/* always@ (posedge conv or posedge rst)`
23			`begin`
24			`if(rst)`
25			`flag <= 0;`
26			`else`
27			`flag <= 1;`
28			`end*/`
29
30			`always@ (posedge clk or posedge rst)`
31			`begin`
32			`if(rst)`
33			`flag <= 0;`
34			`else if (conv)`
35			`flag <= 1;`
36			`else if (count == COUNTMAX)`
37			`begin`
38			`count <= 'b0;`
39			`flag <= 0;`
40			`mem = ~mem;`
41			`end`
42			`end`
43
44			`always @(negedge spi_clk or posedge rst)`
45			`begin`
46			`if (rst)`
47			`count <= 0;`
48			`else if(flag & !rst)`
49			`if(count==COUNTMAX)`
50			`count <= 'b0;`
51			`else`
52			`count <= count+1;`
53			`end`
54
55			`always@(count)`
56			`begin`
57			`case(count)`
58
59			`1 : sdo <= 'bZ;`
60			`2 : sdo <= 'bZ;`
61			`3 : sdo <= mem[13];`
62			`4 : sdo <= mem[12];`
63			`5 : sdo <= mem[11];`
64			`6 : sdo <= mem[10];`
65			`7 : sdo <= mem[9];`
66			`8 : sdo <= mem[8];`
67			`9 : sdo <= mem[7];`
68			`10 : sdo <= mem[6];`
69			`11 : sdo <= mem[5];`
70			`12 : sdo <= mem[4];`
71			`13 : sdo <= mem[3];`
72			`14 : sdo <= mem[2];`
73			`15 : sdo <= mem[1];`
74			`16 : sdo <= mem[0];`
75			`17 : sdo <= 'bZ;`
76			`18 : sdo <= 'bZ;`
77			`19 : sdo <= mem[13];`
78			`20 : sdo <= mem[12];`
79			`21 : sdo <= mem[11];`
80			`22 : sdo <= mem[10];`
81			`23 : sdo <= mem[9];`
82			`24 : sdo <= mem[8];`
83			`25 : sdo <= mem[7];`
84			`26 : sdo <= mem[6];`
85			`27 : sdo <= mem[5];`
86			`28 : sdo <= mem[4];`
87			`29 : sdo <= mem[3];`
88			`30 : sdo <= mem[2];`
89			`31 : sdo <= mem[1];`
90			`32 : sdo <= mem[0];`
91			`33 : sdo <= 'bZ;`
92			`34 : sdo <= 'bZ;`
93			`default: sdo <= 'bZ;`
94			`endcase`
95			`end`
96
97			`endmodule`

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[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [adc.v] - Blame information for rev 2