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URL https://opencores.org/ocsvn/spi_core_dsp_s3ean_kits/spi_core_dsp_s3ean_kits/trunk

Subversion Repositories spi_core_dsp_s3ean_kits

[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [dac.v] - Blame information for rev 2

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1 2 williamgib
module dac(spi_clk, reset, cs, din, dout, command, dacN, dacDATA);
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        parameter Tp = 1;
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        input spi_clk, reset, cs, din;
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        output [3:0]     command;
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        output [3:0]     dacN;
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        output [11:0]    dacDATA;
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        output dout;
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        reg [0:31] data;
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        reg dout;
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        reg temp;
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        assign command = data [0:3];
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        assign dacN = data [4:7];
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        assign dacDATA = data [8:19];
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        always @(posedge spi_clk or posedge reset)
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        begin
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                if(reset)
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                begin
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                        temp <= 1'b0;
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                        data <= 'b0;
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                end
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                else if(!cs)
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                begin
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                        data <= #Tp  {din,data[0:30]};
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                        temp <= #Tp  data[31];
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                end
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        end
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        always @(negedge spi_clk)
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                dout <= #Tp data[31];
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endmodule

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