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[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [spi_top.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  spi_top.v                                                   ////
////                                                              ////
////  This file is part of the SPI IP core project                ////
////  http://www.opencores.org/projects/spi/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot (simons@opencores.org)                     ////
////      - William Gibb (williamgibb@gmail.com)                  ////
////                    Modified to break RX and TX up                                    ////
////                    Fixed TX Width of 24 Bits                         ////
////            Fixed RX Width for LTC ADC on S3A/S3AN Starter Kit////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2002 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "spi_defines.v"
`include "timescale.v"
 
module spi_top
(
        // Input
 clk, rst, ampDAC, data_in, load_div, load_ctrl,
        // output 
        go, chanA, chanB, adcValid,
  // SPI signals
  ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i, conv
);
 
        parameter Tp = 1; //assume register transactions will take some time...
        parameter MAXCOUNT = 24;
        parameter CONVCOUNT = 12;
 
 
        input                   clk;            // master system clock
        input                   rst;            // synchronous active high reset
        input                   ampDAC;         // ampDAC chip select signal, used to select between
                                                                // sending data to the preamp and DAC
        input   [23:0]   data_in;        // data input
        input                   load_ctrl;      // load the ctrl register
        input                   load_div;       // load the divider
 
        output                          go;                     // go! signal
        output          [13:0]   chanA;          // adc channelB
        output          [13:0]   chanB;          // adc channelA
        output                          adcValid;       // data valid output signal
 
 
  // SPI signals
        output  [1:0]    ss_pad_o;       // spi slave select
        output                  conv;           // ADC sampling signal
        output                  sclk_pad_o;     // serial clock
        output                  mosi_pad_o; // master out slave in
        input                   miso_pad_i; // master in slave out                      
 
//  reg                     [27:0] dat_o;
//  reg                              wb_ack_o;
 
 
  // Internal signals
        reg       [`SPI_DIVIDER_LEN-1:0]         divider;          // Divider register
        reg       [`SPI_CTRL_BIT_NB-1:0]         ctrl;             // Control and status register
        reg                                     [1:0]    ss;                     // Slave select register
        reg                                     [1:0]            Q;                              //reg for delaying the go signal two cycles for the adc
        reg                                     [5:0]            Qcount;
        reg                                                                     adcValid;                       //rw data signal
        wire    [`SPI_ADC_CHAR-1:0]              adcData; //data_out
        wire                                    rx_negedge;       // miso is sampled on negative edge
        wire                                    tx_negedge;       // mosi is driven on negative edge
        wire    [`SPI_CHAR_LEN_BITS-1:0]         char_len;         // char len
        wire                                    go;               // go
        wire                                    goRX;             // goRX
        wire                                    goTX;             // goTX
        wire                                    lsb;              // lsb first on line
        wire                                    tip;              // transfer in progress
        wire                                    tipRX;            // transfer in progress, exclusive RX
        wire                                    tipTX;            // transfer in progress, exclusive TX
        wire                                    pos_edge;         // recognize posedge of sclk
        wire                                    neg_edge;         // recognize negedge of sclk
        wire                                    last_bitTX;       // marks last character bit TX
        wire                                    last_bitRX;       // marks last character bit RX
        wire                                    last_bit;         // marks last character bit
        wire                                                            amp;
        wire                                                            dac;
        wire                                                            tx_capture;
        reg                                                                     conv;
        wire                                                            Write;
        wire                                                            Sample;
        reg                                                                     stop;
 
        /*
        TODO LIST
 
        ADD THE SPI RX PORTION
        DONE----INSTANTIATE SPI_SHIFT_IN
        DONE----SPLIT UP CONTROL SIGNALS THAT CONTROL THE TX FROM THE CONTROL SIGNALS
                WHICH WILL CONTROL THE RX
        DONE----MAKE TIP BE FEED BY TWO SEPARATE TIP SIGNALS, TIPRX  TIPTX
                ====THIS WILL LET SPI_CLGEN KEEP RUNNING IF TX FINISHES FIRST
        DONE----KEEP GO AS A SPI ENABLE SIGNAL, HAVE IT ENABLE THE APPROPRIATE MODULE
                BY USING THE WRITE/SAMPLE SIGNAL WITH AN AND GATE
        DONE----ADD A PULSE COUNTER, PARAMETERIZED TO GENERATE CONV PULSE
        DONE----ADD A DATA_VALID SIGNAL TO ENABLE THE READING OF THE DATA OUTPUT
        DONE----SPLIT THE OUTPUT OF THE RX INTO TWO CHANNELS
        */
 
        // Divider register
        always @(posedge clk or posedge rst)
        begin
                if (rst)
                        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
                else if (load_div && !tip)
                        divider <= #Tp data_in[`SPI_DIVIDER_LEN-1:0];
        end
 
        // Ctrl register
        always @(posedge clk or posedge rst)
                begin
                        if (rst)
                        begin
                                ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
                                $display ("Reseting CTRL Register");
                        end
                        else if(load_ctrl && !tip)
                        begin
                                ctrl[`SPI_CTRL_BIT_NB-1:0]       <= #Tp data_in[`SPI_CTRL_BIT_NB-1:0];
                                $display ("Capturing data to CTRL Register");
                                end
                        else
                        begin
                                if(tip && last_bitTX && pos_edge)
                                        begin
                                        ctrl[`SPI_CTRL_WRITE]           <= #Tp 1'b0;
                                        $display ("clearing WRITE on CTRL Register");
                                        end
                                if(tip && last_bitRX && pos_edge)
                                        begin
                                        ctrl[`SPI_CTRL_SAMPLE]          <= #Tp 1'b0;
                                        $display ("clearing SAMPLE on CTRL Register");
                                        end
                                if(tip && last_bit && pos_edge)
                                begin
                                        ctrl[`SPI_CTRL_GO]                      <= #Tp 1'b0;
                                        $display ("clearing GO on CTRL Register");
                                end
                                if(tx_capture)
                                begin
                                        ctrl[`SPI_CTRL_TXC]             <= #Tp 1'b0;
                                        $display ("clearing TXC on CTRL Register");
                                end
                        end
                end
 
        assign rx_negedge       = ctrl[`SPI_CTRL_RX_NEGEDGE];
        assign tx_negedge       = ctrl[`SPI_CTRL_TX_NEGEDGE];
        assign go               = ctrl[`SPI_CTRL_GO];
        assign char_len         = ctrl[`SPI_CTRL_CHAR_LEN];
        assign lsb              = ctrl[`SPI_CTRL_LSB];
        assign Sample           = ctrl[`SPI_CTRL_SAMPLE];
        assign tx_capture       = ctrl[`SPI_CTRL_TXC];
        assign Write            = ctrl[`SPI_CTRL_WRITE];
 
        assign goTX                     = go && Write;
        assign tip                      = tipRX || tipTX;
        assign last_bit         = Sample ? last_bitRX : last_bitTX;
 
        always@(posedge clk or posedge rst)
        begin
                if(rst)
                        Qcount <= #Tp 'b0;
                else if (!stop &&Sample && go)
                        Qcount <= #Tp Qcount + 1;
                else if (tip && last_bitRX && pos_edge)
                        Qcount <= #Tp 'b0;
        end
 
        always@(posedge clk or posedge rst)
        begin
                if(rst)
                        stop <= #Tp 0;
                else if (Qcount == MAXCOUNT)
                        stop <= #Tp 1;
                else if (tip && last_bitRX && pos_edge)
                        stop <= #Tp 0;
        end
 
        always@(posedge clk or posedge rst)
        begin
                if(rst)
                        conv <= #Tp 0;
                else if (Qcount == CONVCOUNT)
                        conv <= #Tp 1;
                else if (Qcount == MAXCOUNT)
                        conv <= #Tp 0;
        end
 
 
        // RX go signal generation
        assign goRX = Q[1] && Sample;
        always@(posedge clk or posedge rst)
        begin
                if(rst)
                        Q<= #Tp 'b0;
                else if(pos_edge && Sample)
                        Q<= #Tp {Q[0], go};
                else if(!Sample)
                begin
                        Q<= #Tp 'b0;
                end
        end
 
        assign amp= !(!ampDAC && go);
        assign dac=     !(ampDAC && go);
        //assign cs signals
        always @(posedge clk or posedge rst)
        begin
                if (rst)
                        ss <= #Tp 2'b11;
                else if(goTX && !tip && Write)
                        ss <= #Tp {amp, dac}; //cs order -> amp, dac
                else if(last_bitTX )
                        ss <= #Tp 2'b11;
                else
                        ss <= #Tp ss;
        end
 
        // data out signal generation
        assign chanA = adcData[30:17];
        assign chanB = adcData[14:1];
        always@(posedge clk or posedge rst)
        begin
                if(rst)
                        adcValid<= #Tp 0;
                else if(!tip)
                        adcValid<= #Tp 0;
                else if(last_bitRX && pos_edge)
                        adcValid<= #Tp 1;
        end
 
/*      always@(posedge clk or posedge rst)
        begin
                if(rst)
                        adcValid<= #Tp 0;
                else if(tip && last_bitRX && pos_edge)
                        adcValid<= #Tp 0;
                else if(last_bitRX && Sample)
                        adcValid<= #Tp 1;
        end*/
 
        assign ss_pad_o = ss;
        spi_clgen clgen (.clk_in(clk), .rst(rst), .go(go), .enable(go&&(Sample||Write)), .last_clk(last_bit),
                   .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
                   .neg_edge(neg_edge));
 
        spi_shift_out tx_shift (.clk(clk), .rst(rst), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
                   .lsb(lsb), .go(goTX), .capture(tx_capture), .pos_edge(pos_edge), .neg_edge(neg_edge),
                   .tx_negedge(tx_negedge), .tip(tipTX), .last(last_bitTX), .p_in(data_in),
                                   .s_out(mosi_pad_o));
 
        spi_shift_in rx_shifter (.clk(clk), .rst(rst), .go(goRX),
                  .pos_edge(pos_edge), .neg_edge(neg_edge), .rx_negedge(rx_negedge),
                 .tip(tipRX), .last(last_bitRX), .p_out(adcData), .s_clk(sclk_pad_o), .s_in(miso_pad_i));
 
endmodule
/*
module spi_shift_out (clk, rst, byte_sel, len, lsb, go,
                  pos_edge, neg_edge, tx_negedge,
                  tip, last,
                  p_in, s_clk, s_out);
 
module spi_shift_in (.clk(), .rst(), .lsb(), .go,
                  pos_edge(), .neg_edge(), .rx_negedge(), .tx_negedge,
                  tip(), .last(), .p_out(), .s_clk(), .s_in());
*/

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Subversion Repositories spi_core_dsp_s3ean_kits

[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [spi_top.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	williamgib	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// spi_top.v ////`
4			`//// ////`
5			`//// This file is part of the SPI IP core project ////`
6			`//// http://www.opencores.org/projects/spi/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Simon Srot (simons@opencores.org) ////`
10			`//// - William Gibb (williamgibb@gmail.com) ////`
11			`//// Modified to break RX and TX up ////`
12			`//// Fixed TX Width of 24 Bits ////`
13			`//// Fixed RX Width for LTC ADC on S3A/S3AN Starter Kit////`
14			`//// ////`
15			`//// All additional information is avaliable in the Readme.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2002 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44
45
46			`include "spi_defines.v"
47			`include "timescale.v"
48
49			`module spi_top`
50			`(`
51			`// Input`
52			`clk, rst, ampDAC, data_in, load_div, load_ctrl,`
53			`// output`
54			`go, chanA, chanB, adcValid,`
55			`// SPI signals`
56			`ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i, conv`
57			`);`
58
59			`parameter Tp = 1; //assume register transactions will take some time...`
60			`parameter MAXCOUNT = 24;`
61			`parameter CONVCOUNT = 12;`
62
63
64			`input clk; // master system clock`
65			`input rst; // synchronous active high reset`
66			`input ampDAC; // ampDAC chip select signal, used to select between`
67			`// sending data to the preamp and DAC`
68			`input [23:0] data_in; // data input`
69			`input load_ctrl; // load the ctrl register`
70			`input load_div; // load the divider`
71
72			`output go; // go! signal`
73			`output [13:0] chanA; // adc channelB`
74			`output [13:0] chanB; // adc channelA`
75			`output adcValid; // data valid output signal`
76
77
78			`// SPI signals`
79			`output [1:0] ss_pad_o; // spi slave select`
80			`output conv; // ADC sampling signal`
81			`output sclk_pad_o; // serial clock`
82			`output mosi_pad_o; // master out slave in`
83			`input miso_pad_i; // master in slave out`
84
85			`// reg [27:0] dat_o;`
86			`// reg wb_ack_o;`
87
88
89			`// Internal signals`
90			reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register
91			reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
92			`reg [1:0] ss; // Slave select register`
93			`reg [1:0] Q; //reg for delaying the go signal two cycles for the adc`
94			`reg [5:0] Qcount;`
95			`reg adcValid; //rw data signal`
96			wire [`SPI_ADC_CHAR-1:0] adcData; //data_out
97			`wire rx_negedge; // miso is sampled on negative edge`
98			`wire tx_negedge; // mosi is driven on negative edge`
99			wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
100			`wire go; // go`
101			`wire goRX; // goRX`
102			`wire goTX; // goTX`
103			`wire lsb; // lsb first on line`
104			`wire tip; // transfer in progress`
105			`wire tipRX; // transfer in progress, exclusive RX`
106			`wire tipTX; // transfer in progress, exclusive TX`
107			`wire pos_edge; // recognize posedge of sclk`
108			`wire neg_edge; // recognize negedge of sclk`
109			`wire last_bitTX; // marks last character bit TX`
110			`wire last_bitRX; // marks last character bit RX`
111			`wire last_bit; // marks last character bit`
112			`wire amp;`
113			`wire dac;`
114			`wire tx_capture;`
115			`reg conv;`
116			`wire Write;`
117			`wire Sample;`
118			`reg stop;`
119
120			`/*`
121			`TODO LIST`
122
123			`ADD THE SPI RX PORTION`
124			`DONE----INSTANTIATE SPI_SHIFT_IN`
125			`DONE----SPLIT UP CONTROL SIGNALS THAT CONTROL THE TX FROM THE CONTROL SIGNALS`
126			`WHICH WILL CONTROL THE RX`
127			`DONE----MAKE TIP BE FEED BY TWO SEPARATE TIP SIGNALS, TIPRX TIPTX`
128			`====THIS WILL LET SPI_CLGEN KEEP RUNNING IF TX FINISHES FIRST`
129			`DONE----KEEP GO AS A SPI ENABLE SIGNAL, HAVE IT ENABLE THE APPROPRIATE MODULE`
130			`BY USING THE WRITE/SAMPLE SIGNAL WITH AN AND GATE`
131			`DONE----ADD A PULSE COUNTER, PARAMETERIZED TO GENERATE CONV PULSE`
132			`DONE----ADD A DATA_VALID SIGNAL TO ENABLE THE READING OF THE DATA OUTPUT`
133			`DONE----SPLIT THE OUTPUT OF THE RX INTO TWO CHANNELS`
134			`*/`
135
136			`// Divider register`
137			`always @(posedge clk or posedge rst)`
138			`begin`
139			`if (rst)`
140			divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
141			`else if (load_div && !tip)`
142			divider <= #Tp data_in[`SPI_DIVIDER_LEN-1:0];
143			`end`
144
145			`// Ctrl register`
146			`always @(posedge clk or posedge rst)`
147			`begin`
148			`if (rst)`
149			`begin`
150			ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
151			`$display ("Reseting CTRL Register");`
152			`end`
153			`else if(load_ctrl && !tip)`
154			`begin`
155			ctrl[`SPI_CTRL_BIT_NB-1:0] <= #Tp data_in[`SPI_CTRL_BIT_NB-1:0];
156			`$display ("Capturing data to CTRL Register");`
157			`end`
158			`else`
159			`begin`
160			`if(tip && last_bitTX && pos_edge)`
161			`begin`
162			ctrl[`SPI_CTRL_WRITE] <= #Tp 1'b0;
163			`$display ("clearing WRITE on CTRL Register");`
164			`end`
165			`if(tip && last_bitRX && pos_edge)`
166			`begin`
167			ctrl[`SPI_CTRL_SAMPLE] <= #Tp 1'b0;
168			`$display ("clearing SAMPLE on CTRL Register");`
169			`end`
170			`if(tip && last_bit && pos_edge)`
171			`begin`
172			ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
173			`$display ("clearing GO on CTRL Register");`
174			`end`
175			`if(tx_capture)`
176			`begin`
177			ctrl[`SPI_CTRL_TXC] <= #Tp 1'b0;
178			`$display ("clearing TXC on CTRL Register");`
179			`end`
180			`end`
181			`end`
182
183			assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
184			assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
185			assign go = ctrl[`SPI_CTRL_GO];
186			assign char_len = ctrl[`SPI_CTRL_CHAR_LEN];
187			assign lsb = ctrl[`SPI_CTRL_LSB];
188			assign Sample = ctrl[`SPI_CTRL_SAMPLE];
189			assign tx_capture = ctrl[`SPI_CTRL_TXC];
190			assign Write = ctrl[`SPI_CTRL_WRITE];
191
192			`assign goTX = go && Write;`
193			`assign tip = tipRX \|\| tipTX;`
194			`assign last_bit = Sample ? last_bitRX : last_bitTX;`
195
196			`always@(posedge clk or posedge rst)`
197			`begin`
198			`if(rst)`
199			`Qcount <= #Tp 'b0;`
200			`else if (!stop &&Sample && go)`
201			`Qcount <= #Tp Qcount + 1;`
202			`else if (tip && last_bitRX && pos_edge)`
203			`Qcount <= #Tp 'b0;`
204			`end`
205
206			`always@(posedge clk or posedge rst)`
207			`begin`
208			`if(rst)`
209			`stop <= #Tp 0;`
210			`else if (Qcount == MAXCOUNT)`
211			`stop <= #Tp 1;`
212			`else if (tip && last_bitRX && pos_edge)`
213			`stop <= #Tp 0;`
214			`end`
215
216			`always@(posedge clk or posedge rst)`
217			`begin`
218			`if(rst)`
219			`conv <= #Tp 0;`
220			`else if (Qcount == CONVCOUNT)`
221			`conv <= #Tp 1;`
222			`else if (Qcount == MAXCOUNT)`
223			`conv <= #Tp 0;`
224			`end`
225
226
227			`// RX go signal generation`
228			`assign goRX = Q[1] && Sample;`
229			`always@(posedge clk or posedge rst)`
230			`begin`
231			`if(rst)`
232			`Q<= #Tp 'b0;`
233			`else if(pos_edge && Sample)`
234			`Q<= #Tp {Q[0], go};`
235			`else if(!Sample)`
236			`begin`
237			`Q<= #Tp 'b0;`
238			`end`
239			`end`
240
241			`assign amp= !(!ampDAC && go);`
242			`assign dac= !(ampDAC && go);`
243			`//assign cs signals`
244			`always @(posedge clk or posedge rst)`
245			`begin`
246			`if (rst)`
247			`ss <= #Tp 2'b11;`
248			`else if(goTX && !tip && Write)`
249			`ss <= #Tp {amp, dac}; //cs order -> amp, dac`
250			`else if(last_bitTX )`
251			`ss <= #Tp 2'b11;`
252			`else`
253			`ss <= #Tp ss;`
254			`end`
255
256			`// data out signal generation`
257			`assign chanA = adcData[30:17];`
258			`assign chanB = adcData[14:1];`
259			`always@(posedge clk or posedge rst)`
260			`begin`
261			`if(rst)`
262			`adcValid<= #Tp 0;`
263			`else if(!tip)`
264			`adcValid<= #Tp 0;`
265			`else if(last_bitRX && pos_edge)`
266			`adcValid<= #Tp 1;`
267			`end`
268
269			`/* always@(posedge clk or posedge rst)`
270			`begin`
271			`if(rst)`
272			`adcValid<= #Tp 0;`
273			`else if(tip && last_bitRX && pos_edge)`
274			`adcValid<= #Tp 0;`
275			`else if(last_bitRX && Sample)`
276			`adcValid<= #Tp 1;`
277			`end*/`
278
279			`assign ss_pad_o = ss;`
280			`spi_clgen clgen (.clk_in(clk), .rst(rst), .go(go), .enable(go&&(Sample\|\|Write)), .last_clk(last_bit),`
281			`.divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),`
282			`.neg_edge(neg_edge));`
283
284			spi_shift_out tx_shift (.clk(clk), .rst(rst), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
285			`.lsb(lsb), .go(goTX), .capture(tx_capture), .pos_edge(pos_edge), .neg_edge(neg_edge),`
286			`.tx_negedge(tx_negedge), .tip(tipTX), .last(last_bitTX), .p_in(data_in),`
287			`.s_out(mosi_pad_o));`
288
289			`spi_shift_in rx_shifter (.clk(clk), .rst(rst), .go(goRX),`
290			`.pos_edge(pos_edge), .neg_edge(neg_edge), .rx_negedge(rx_negedge),`
291			`.tip(tipRX), .last(last_bitRX), .p_out(adcData), .s_clk(sclk_pad_o), .s_in(miso_pad_i));`
292
293			`endmodule`
294			`/*`
295			`module spi_shift_out (clk, rst, byte_sel, len, lsb, go,`
296			`pos_edge, neg_edge, tx_negedge,`
297			`tip, last,`
298			`p_in, s_clk, s_out);`
299
300			`module spi_shift_in (.clk(), .rst(), .lsb(), .go,`
301			`pos_edge(), .neg_edge(), .rx_negedge(), .tx_negedge,`
302			`tip(), .last(), .p_out(), .s_clk(), .s_in());`
303			`*/`