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Subversion Repositories spi_core_dsp_s3ean_kits

[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [spi_top_tb2.v] - Blame information for rev 2

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`include "timescale.v"
`include "spi_defines.v"
//      spi_top tb
module spi_top_tb2();
 
        //
        // FOR SPI_TOP COMPLETED SUNDAY NOV 15th
        //
 
        //parameters
        parameter CLKPERIOD = 20;
        //
        // Control words
        //
 
        parameter CTRL_PREP             =       14'h0E18; //TXC=0, SAMPLE = 0,| LSB=1, TXN=1, RXN=1, GO=0,| WR=0, LEN=24bits
        parameter CTRL_TXC              =       14'h2E18; //TXC=1, SAMPLE = 0,| LSB=1, TXN=1, RXN=1, GO=0,| WR=0, LEN=24bits 
        parameter CTRL_GOSAMPLE =       14'h1F18; //TXC=0, SAMPLE = 1,| LSB=1, TXN=1, RXN=1, GO=1,| WR=0, LEN=24bits
        parameter CTRL_GOWRITE  =       14'h0F98; //TXC=0, SAMPLE = 0,| LSB=1, TXN=1, RXN=1, GO=1,| WR=1, LEN=24bits
        parameter CTRL_GOALL    =       14'h1F98; //TXC=0, SAMPLE = 1,| LSB=1, TXN=1, RXN=1, GO=1,| WR=1, LEN=24bits
 
        parameter DIV_VALUE             =       24'h000010; //dec 16
 
        parameter DAC_A                 =       4'h0; // choose dac A
        parameter DAC_COMMAND   =       4'h3; // write to adn update dac n
        parameter FINISHTIME    =       186*1000; //17 ns per write...
 
        // dut inputs
        reg clk;
        reg rst;
        reg ampDAC;
        reg load_div;
        reg load_ctrl;
        reg [23:0] data_in;
        // interconnect wires
        wire spi_mosi;
        wire amp_miso;
        wire dac_miso;
        wire adc_miso;
        wire spi_clk;
        wire [1:0] ss_o;
        wire conv;
 
        reg fin, fin1;
        reg [23:0] data_tbw; //data to be written
        reg [11:0] dac_data_in;
 
        //output wires
        wire [7:0]       gain_state;
        wire [3:0]       dac_command;
        wire [3:0]       dac_n;
        wire [11:0] dac_data;
        wire            go;
        wire [13:0] chanA;
        wire [13:0] chanB;
        wire            adcValid;
 
        // events
        event write_command, reset, write_div, write_dac, write_amp, read_adc, rw_DSP;
 
        // dut outputs
 
        /*
        // dut
        /*spi_top spi_core (.clk(), .rst(), .ampDAC(), .data_in(), .chanA(), .chanB(), .adcValud(), .load_div(),
                        .load_ctrl(), . go(), .conv, ss_pad_o(),
                        .sclk_pad_o(), .mosi_pad_o(), .miso_pad_i()); */
        spi_top spi_core (.clk(clk),
                                        .rst(rst),
                                        .ampDAC(ampDAC),
                                        .data_in(data_in),
                                        .chanA(chanA),
                                        .chanB(chanB),
                                        .adcValid(adcValid),
                                        .load_div(load_div),
                                        .load_ctrl(load_ctrl),
                                        .go(go),
                                        .conv(conv),
                                        .ss_pad_o(ss_o),
                                        .sclk_pad_o(spi_clk),
                                        .mosi_pad_o(spi_mosi),
                                        .miso_pad_i(adc_miso));
 
        // spi models
        // dac(.spi_clk(), .reset(), .cs(), .din(), .dout(), .command(), .dacN(), .dacDATA());
        // amp(.spi_clk(), .reset(), .cs(), .din(), .dout(), .gain_state());
        // adc(.sdo(), .spi_clk(), .clk(), .rst(), .conv() );
        dac dac_test (.spi_clk(spi_clk),
        .reset(rst), .cs(ss_o[0]), .din(spi_mosi),
                                        .dout(dac_miso),
                                        .command(dac_command),
                                        .dacN(dac_n),
                                        .dacDATA(dac_data));
        amp amp_test (.spi_clk(spi_clk),
                                        .reset(rst),
                                        .cs(ss_o[1]),
                                        .din(spi_mosi),
                                        .dout(amp_miso),
                                        .gain_state(gain_state));
        adc adc_test(.sdo(adc_miso),
                                        .spi_clk(spi_clk),
                                        .clk(clk),
                                        .rst(rst),
                                        .conv(conv));
        // dut stimulus
        // 1 reset
        // 2 write the divider
        // 3 write the control
        // 4 write a word to the amp
        // 5 write a word to the dac
        // 6 read a word from the adc
        // 6 write a procedure for checking the words written
 
        //clk
        always
                #(CLKPERIOD/2) clk = ~clk;
 
        //initial conditions
        initial
        begin
                load_div        =0;
                load_ctrl       =0;
                clk                     =1;
                ampDAC          =0;
                rst                     =0;
                fin             =0;
                fin1            =0;
                data_in         =24'b0;
                dac_data_in     ='b0;
                #FINISHTIME ;
                $display ("Finishing simulation due to simulation constraint.");
                $display ("Time is - %d",$time);
                $finish;
        end
 
        // CTRL_PREP            TXC=0, SAMPLE = 0,| LSB=1, TXN=1, RXN=1, GO=0,| WR=0, LEN=24bits
        // CTRL_TXC                     TXC=1, SAMPLE = 0,| LSB=1, TXN=1, RXN=1, GO=0,| WR=0, LEN=24bits 
        // CTRL_GOSAMPLE        TXC=0, SAMPLE = 1,| LSB=1, TXN=1, RXN=1, GO=1,| WR=0, LEN=24bits
        // CTRL_GOWRITE         TXC=0, SAMPLE = 0,| LSB=1, TXN=1, RXN=1, GO=1,| WR=1, LEN=24bits
        // CTRL_GOALL           TXC=0, SAMPLE = 1,| LSB=1, TXN=1, RXN=1, GO=1,| WR=1, LEN=24bits
        // events: write_command, reset, write_div, write_word;
 
        //event ordering
        initial
        begin
                $display("Starting simulation");
                #CLKPERIOD      -> reset;
                wait(fin)
                fin =0;
 
                $display("Reset finished");
                data_in=CTRL_PREP;
                #CLKPERIOD      -> write_command;
                wait(fin)
                fin =0;
 
                data_in=DIV_VALUE;
                #CLKPERIOD  -> write_div;
                wait(fin)
                fin =0;
 
                data_tbw =24'h110000; //write 0x11 to AMP
                #CLKPERIOD      -> write_amp;
                wait(fin)
                fin =0;
 
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> write_dac;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> write_dac;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> write_dac;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> write_dac;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> write_dac;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> write_dac;
                wait(fin)
                fin =0;
                #CLKPERIOD      -> read_adc;
                wait(fin)
                fin =0;
                #CLKPERIOD      -> read_adc;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> rw_DSP;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> rw_DSP;
                wait(fin)
                fin =0;
                dac_data_in=dac_data_in+1;
                data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};
                #CLKPERIOD      -> rw_DSP;
                wait(fin)
                fin =0;
 
                #CLKPERIOD;
                #CLKPERIOD;
                $display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
                $display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
                #CLKPERIOD;
                $display("Finishing up at time %7d", $time);
                $display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
                $display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
 
                $finish;
        end
 
        //event definitions
        always @(reset)
        begin
                $display ("entering reset at time %6d",$time);
                #10;
                rst=1;
                #100;
                rst=0;
                $display ("leaving event at time %6d",$time);
                fin =1;
        end
 
        always @(write_div)
        begin
                $display("writing value %3d to divider register",data_in);
                load_div=1;
                #CLKPERIOD;
                load_div=0;
                $display("leaving write_div at time %6d",$time);
                fin =1;
        end
 
        always @(write_command)
        begin
                $display("writing word %4h to control register",data_in);
                load_ctrl=1;
                #CLKPERIOD;
                load_ctrl=0;
                $display("leaving write_command at time %6d",$time);
                fin =1;
        end
 
        always @(write_amp)
        begin
                $display("writing word %4h to tx AMP at time %6d",data_tbw, $time);
                data_in = CTRL_TXC;
                $display("writing word %4h to control register",data_in);
                load_ctrl=1;
                #CLKPERIOD;
                load_ctrl=0;
                $display ("returned to write_word event at time %5d",$time);
                data_in = data_tbw;
                #CLKPERIOD;
                load_ctrl=1;
                ampDAC =0;
                data_in = CTRL_GOWRITE;
                #CLKPERIOD;
                load_ctrl=0;
                $display("waiting for go to go low...");
                wait(!go)
                $display("go went low at time %6d",$time);
                #CLKPERIOD;
                fin =1;
        end
 
        always @(write_dac)
        begin
                $display("writing word %4h to tx DAC at time %6d",data_tbw, $time);
                data_in = CTRL_TXC;
                $display("writing word %4h to control register",data_in);
                load_ctrl=1;
                #CLKPERIOD;
                load_ctrl=0;
                $display ("returned to write_word event at time %6d",$time);
                data_in = data_tbw;
                #CLKPERIOD;
                load_ctrl=1;
                ampDAC =1;
                data_in = CTRL_GOWRITE;
                #CLKPERIOD;
                load_ctrl=0;
                $display("waiting for go to go low...");
                wait(!go)
                $display("go went low at time %6d",$time);
                #CLKPERIOD;
                fin =1;
        end
 
        always @(read_adc)
        begin
                $display ("Reading from the ADC");
                #CLKPERIOD;
                load_ctrl=1;
                data_in = CTRL_GOSAMPLE;
                #CLKPERIOD;
                load_ctrl=0;
                #2;
                $display("waiting for go to go low...");
                wait(!go)
                $display("go went low at time %6d",$time);
                #CLKPERIOD;
                fin =1;
        end
 
        always @(rw_DSP)
        begin
                $display("writing word %4h to tx DAC and SAMPLING at time %6d",data_tbw, $time);
                data_in = CTRL_TXC;
                $display("writing word %4h to control register",data_in);
                load_ctrl=1;
                #CLKPERIOD;
                load_ctrl=0;
                $display ("returned to write_word event at time %6d",$time);
                data_in = data_tbw;
                #CLKPERIOD;
                load_ctrl=1;
                ampDAC =1;
                data_in = CTRL_GOALL;
                #CLKPERIOD;
                load_ctrl=0;
                $display("waiting for go to go low...");
                #2;
                wait(!go)
                $display("go went low at time %6d",$time);
                #CLKPERIOD;
                fin =1;
        end
        //monitor
        //dump the activity
        initial
        begin
                $dumpfile ("waves.vcd");
                $dumpvars(0,spi_top_tb2);
        end
 
endmodule

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Subversion Repositories spi_core_dsp_s3ean_kits

[/] [spi_core_dsp_s3ean_kits/] [trunk/] [rtl/] [verilog/] [spi_top_tb2.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	williamgib	`include "timescale.v"
2			`include "spi_defines.v"
3			`// spi_top tb`
4			`module spi_top_tb2();`
5
6			`//`
7			`// FOR SPI_TOP COMPLETED SUNDAY NOV 15th`
8			`//`
9
10			`//parameters`
11			`parameter CLKPERIOD = 20;`
12			`//`
13			`// Control words`
14			`//`
15
16			`parameter CTRL_PREP = 14'h0E18; //TXC=0, SAMPLE = 0,\| LSB=1, TXN=1, RXN=1, GO=0,\| WR=0, LEN=24bits`
17			`parameter CTRL_TXC = 14'h2E18; //TXC=1, SAMPLE = 0,\| LSB=1, TXN=1, RXN=1, GO=0,\| WR=0, LEN=24bits`
18			`parameter CTRL_GOSAMPLE = 14'h1F18; //TXC=0, SAMPLE = 1,\| LSB=1, TXN=1, RXN=1, GO=1,\| WR=0, LEN=24bits`
19			`parameter CTRL_GOWRITE = 14'h0F98; //TXC=0, SAMPLE = 0,\| LSB=1, TXN=1, RXN=1, GO=1,\| WR=1, LEN=24bits`
20			`parameter CTRL_GOALL = 14'h1F98; //TXC=0, SAMPLE = 1,\| LSB=1, TXN=1, RXN=1, GO=1,\| WR=1, LEN=24bits`
21
22			`parameter DIV_VALUE = 24'h000010; //dec 16`
23
24			`parameter DAC_A = 4'h0; // choose dac A`
25			`parameter DAC_COMMAND = 4'h3; // write to adn update dac n`
26			`parameter FINISHTIME = 186*1000; //17 ns per write...`
27
28			`// dut inputs`
29			`reg clk;`
30			`reg rst;`
31			`reg ampDAC;`
32			`reg load_div;`
33			`reg load_ctrl;`
34			`reg [23:0] data_in;`
35			`// interconnect wires`
36			`wire spi_mosi;`
37			`wire amp_miso;`
38			`wire dac_miso;`
39			`wire adc_miso;`
40			`wire spi_clk;`
41			`wire [1:0] ss_o;`
42			`wire conv;`
43
44			`reg fin, fin1;`
45			`reg [23:0] data_tbw; //data to be written`
46			`reg [11:0] dac_data_in;`
47
48			`//output wires`
49			`wire [7:0] gain_state;`
50			`wire [3:0] dac_command;`
51			`wire [3:0] dac_n;`
52			`wire [11:0] dac_data;`
53			`wire go;`
54			`wire [13:0] chanA;`
55			`wire [13:0] chanB;`
56			`wire adcValid;`
57
58			`// events`
59			`event write_command, reset, write_div, write_dac, write_amp, read_adc, rw_DSP;`
60
61			`// dut outputs`
62
63			`/*`
64			`// dut`
65			`/*spi_top spi_core (.clk(), .rst(), .ampDAC(), .data_in(), .chanA(), .chanB(), .adcValud(), .load_div(),`
66			`.load_ctrl(), . go(), .conv, ss_pad_o(),`
67			`.sclk_pad_o(), .mosi_pad_o(), .miso_pad_i()); */`
68			`spi_top spi_core (.clk(clk),`
69			`.rst(rst),`
70			`.ampDAC(ampDAC),`
71			`.data_in(data_in),`
72			`.chanA(chanA),`
73			`.chanB(chanB),`
74			`.adcValid(adcValid),`
75			`.load_div(load_div),`
76			`.load_ctrl(load_ctrl),`
77			`.go(go),`
78			`.conv(conv),`
79			`.ss_pad_o(ss_o),`
80			`.sclk_pad_o(spi_clk),`
81			`.mosi_pad_o(spi_mosi),`
82			`.miso_pad_i(adc_miso));`
83
84			`// spi models`
85			`// dac(.spi_clk(), .reset(), .cs(), .din(), .dout(), .command(), .dacN(), .dacDATA());`
86			`// amp(.spi_clk(), .reset(), .cs(), .din(), .dout(), .gain_state());`
87			`// adc(.sdo(), .spi_clk(), .clk(), .rst(), .conv() );`
88			`dac dac_test (.spi_clk(spi_clk),`
89			`.reset(rst), .cs(ss_o[0]), .din(spi_mosi),`
90			`.dout(dac_miso),`
91			`.command(dac_command),`
92			`.dacN(dac_n),`
93			`.dacDATA(dac_data));`
94			`amp amp_test (.spi_clk(spi_clk),`
95			`.reset(rst),`
96			`.cs(ss_o[1]),`
97			`.din(spi_mosi),`
98			`.dout(amp_miso),`
99			`.gain_state(gain_state));`
100			`adc adc_test(.sdo(adc_miso),`
101			`.spi_clk(spi_clk),`
102			`.clk(clk),`
103			`.rst(rst),`
104			`.conv(conv));`
105			`// dut stimulus`
106			`// 1 reset`
107			`// 2 write the divider`
108			`// 3 write the control`
109			`// 4 write a word to the amp`
110			`// 5 write a word to the dac`
111			`// 6 read a word from the adc`
112			`// 6 write a procedure for checking the words written`
113
114			`//clk`
115			`always`
116			`#(CLKPERIOD/2) clk = ~clk;`
117
118			`//initial conditions`
119			`initial`
120			`begin`
121			`load_div =0;`
122			`load_ctrl =0;`
123			`clk =1;`
124			`ampDAC =0;`
125			`rst =0;`
126			`fin =0;`
127			`fin1 =0;`
128			`data_in =24'b0;`
129			`dac_data_in ='b0;`
130			`#FINISHTIME ;`
131			`$display ("Finishing simulation due to simulation constraint.");`
132			`$display ("Time is - %d",$time);`
133			`$finish;`
134			`end`
135
136			`// CTRL_PREP TXC=0, SAMPLE = 0,\| LSB=1, TXN=1, RXN=1, GO=0,\| WR=0, LEN=24bits`
137			`// CTRL_TXC TXC=1, SAMPLE = 0,\| LSB=1, TXN=1, RXN=1, GO=0,\| WR=0, LEN=24bits`
138			`// CTRL_GOSAMPLE TXC=0, SAMPLE = 1,\| LSB=1, TXN=1, RXN=1, GO=1,\| WR=0, LEN=24bits`
139			`// CTRL_GOWRITE TXC=0, SAMPLE = 0,\| LSB=1, TXN=1, RXN=1, GO=1,\| WR=1, LEN=24bits`
140			`// CTRL_GOALL TXC=0, SAMPLE = 1,\| LSB=1, TXN=1, RXN=1, GO=1,\| WR=1, LEN=24bits`
141			`// events: write_command, reset, write_div, write_word;`
142
143			`//event ordering`
144			`initial`
145			`begin`
146			`$display("Starting simulation");`
147			`#CLKPERIOD -> reset;`
148			`wait(fin)`
149			`fin =0;`
150
151			`$display("Reset finished");`
152			`data_in=CTRL_PREP;`
153			`#CLKPERIOD -> write_command;`
154			`wait(fin)`
155			`fin =0;`
156
157			`data_in=DIV_VALUE;`
158			`#CLKPERIOD -> write_div;`
159			`wait(fin)`
160			`fin =0;`
161
162			`data_tbw =24'h110000; //write 0x11 to AMP`
163			`#CLKPERIOD -> write_amp;`
164			`wait(fin)`
165			`fin =0;`
166
167			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
168			`#CLKPERIOD -> write_dac;`
169			`wait(fin)`
170			`fin =0;`
171			`dac_data_in=dac_data_in+1;`
172			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
173			`#CLKPERIOD -> write_dac;`
174			`wait(fin)`
175			`fin =0;`
176			`dac_data_in=dac_data_in+1;`
177			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
178			`#CLKPERIOD -> write_dac;`
179			`wait(fin)`
180			`fin =0;`
181			`dac_data_in=dac_data_in+1;`
182			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
183			`#CLKPERIOD -> write_dac;`
184			`wait(fin)`
185			`fin =0;`
186			`dac_data_in=dac_data_in+1;`
187			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
188			`#CLKPERIOD -> write_dac;`
189			`wait(fin)`
190			`fin =0;`
191			`dac_data_in=dac_data_in+1;`
192			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
193			`#CLKPERIOD -> write_dac;`
194			`wait(fin)`
195			`fin =0;`
196			`#CLKPERIOD -> read_adc;`
197			`wait(fin)`
198			`fin =0;`
199			`#CLKPERIOD -> read_adc;`
200			`wait(fin)`
201			`fin =0;`
202			`dac_data_in=dac_data_in+1;`
203			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
204			`#CLKPERIOD -> rw_DSP;`
205			`wait(fin)`
206			`fin =0;`
207			`dac_data_in=dac_data_in+1;`
208			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
209			`#CLKPERIOD -> rw_DSP;`
210			`wait(fin)`
211			`fin =0;`
212			`dac_data_in=dac_data_in+1;`
213			`data_tbw = {DAC_COMMAND, DAC_A,dac_data_in,4'b0};`
214			`#CLKPERIOD -> rw_DSP;`
215			`wait(fin)`
216			`fin =0;`
217
218			`#CLKPERIOD;`
219			`#CLKPERIOD;`
220			`$display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");`
221			`$display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");`
222			`#CLKPERIOD;`
223			`$display("Finishing up at time %7d", $time);`
224			`$display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");`
225			`$display ("!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");`
226
227			`$finish;`
228			`end`
229
230			`//event definitions`
231			`always @(reset)`
232			`begin`
233			`$display ("entering reset at time %6d",$time);`
234			`#10;`
235			`rst=1;`
236			`#100;`
237			`rst=0;`
238			`$display ("leaving event at time %6d",$time);`
239			`fin =1;`
240			`end`
241
242			`always @(write_div)`
243			`begin`
244			`$display("writing value %3d to divider register",data_in);`
245			`load_div=1;`
246			`#CLKPERIOD;`
247			`load_div=0;`
248			`$display("leaving write_div at time %6d",$time);`
249			`fin =1;`
250			`end`
251
252			`always @(write_command)`
253			`begin`
254			`$display("writing word %4h to control register",data_in);`
255			`load_ctrl=1;`
256			`#CLKPERIOD;`
257			`load_ctrl=0;`
258			`$display("leaving write_command at time %6d",$time);`
259			`fin =1;`
260			`end`
261
262			`always @(write_amp)`
263			`begin`
264			`$display("writing word %4h to tx AMP at time %6d",data_tbw, $time);`
265			`data_in = CTRL_TXC;`
266			`$display("writing word %4h to control register",data_in);`
267			`load_ctrl=1;`
268			`#CLKPERIOD;`
269			`load_ctrl=0;`
270			`$display ("returned to write_word event at time %5d",$time);`
271			`data_in = data_tbw;`
272			`#CLKPERIOD;`
273			`load_ctrl=1;`
274			`ampDAC =0;`
275			`data_in = CTRL_GOWRITE;`
276			`#CLKPERIOD;`
277			`load_ctrl=0;`
278			`$display("waiting for go to go low...");`
279			`wait(!go)`
280			`$display("go went low at time %6d",$time);`
281			`#CLKPERIOD;`
282			`fin =1;`
283			`end`
284
285			`always @(write_dac)`
286			`begin`
287			`$display("writing word %4h to tx DAC at time %6d",data_tbw, $time);`
288			`data_in = CTRL_TXC;`
289			`$display("writing word %4h to control register",data_in);`
290			`load_ctrl=1;`
291			`#CLKPERIOD;`
292			`load_ctrl=0;`
293			`$display ("returned to write_word event at time %6d",$time);`
294			`data_in = data_tbw;`
295			`#CLKPERIOD;`
296			`load_ctrl=1;`
297			`ampDAC =1;`
298			`data_in = CTRL_GOWRITE;`
299			`#CLKPERIOD;`
300			`load_ctrl=0;`
301			`$display("waiting for go to go low...");`
302			`wait(!go)`
303			`$display("go went low at time %6d",$time);`
304			`#CLKPERIOD;`
305			`fin =1;`
306			`end`
307
308			`always @(read_adc)`
309			`begin`
310			`$display ("Reading from the ADC");`
311			`#CLKPERIOD;`
312			`load_ctrl=1;`
313			`data_in = CTRL_GOSAMPLE;`
314			`#CLKPERIOD;`
315			`load_ctrl=0;`
316			`#2;`
317			`$display("waiting for go to go low...");`
318			`wait(!go)`
319			`$display("go went low at time %6d",$time);`
320			`#CLKPERIOD;`
321			`fin =1;`
322			`end`
323
324			`always @(rw_DSP)`
325			`begin`
326			`$display("writing word %4h to tx DAC and SAMPLING at time %6d",data_tbw, $time);`
327			`data_in = CTRL_TXC;`
328			`$display("writing word %4h to control register",data_in);`
329			`load_ctrl=1;`
330			`#CLKPERIOD;`
331			`load_ctrl=0;`
332			`$display ("returned to write_word event at time %6d",$time);`
333			`data_in = data_tbw;`
334			`#CLKPERIOD;`
335			`load_ctrl=1;`
336			`ampDAC =1;`
337			`data_in = CTRL_GOALL;`
338			`#CLKPERIOD;`
339			`load_ctrl=0;`
340			`$display("waiting for go to go low...");`
341			`#2;`
342			`wait(!go)`
343			`$display("go went low at time %6d",$time);`
344			`#CLKPERIOD;`
345			`fin =1;`
346			`end`
347			`//monitor`
348			`//dump the activity`
349			`initial`
350			`begin`
351			`$dumpfile ("waves.vcd");`
352			`$dumpvars(0,spi_top_tb2);`
353			`end`
354
355			`endmodule`