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[/] [spi_master/] [trunk/] [hw/] [simulations/] [Testbench_SPIMaster_behav.wcfg] - Blame information for rev 2

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      clock_12M
      clock_12M
   
   
      reset
      reset
   
   
      cpol
      cpol
   
   
      cpha
      cpha
   
   
      start
      start
   
   
      i_write_value[7:0]
      i_write_value[7:0]
      BINARYRADIX
   
   
      state
      state
   
   
      clock_divider
      clock_divider
   
   
      clock_enable
      clock_enable
   
   
      clock_enable_x2
      clock_enable_x2
   
   
      bit_counter[3:0]
      bit_counter[3:0]
      HEXRADIX
   
   
      bit_counter_end
      bit_counter_end
   
   
      delay_counter_end
      delay_counter_end
   
   
      byte_counter_end
      byte_counter_end
   
   
      sclk
      sclk
   
   
      write_value_reg[7:0]
      write_value_reg[7:0]
      BINARYRADIX
   
   
      mosi
      mosi
   
   
      miso
      miso
   
   
      read_value[7:0]
      read_value[7:0]
      BINARYRADIX
   
   
      read_value_valid
      read_value_valid
   
   
      ready
      ready
   
   
      busy
      busy
   
   
      ss[0:0]
      ss[0:0]
   


Line No.	Rev	Author	Line
1	2	ldalmasso
2
3
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5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24			`clock_12M`
25			`clock_12M`
26
27
28			`reset`
29			`reset`
30
31
32			`cpol`
33			`cpol`
34
35
36			`cpha`
37			`cpha`
38
39
40			`start`
41			`start`
42
43
44			`i_write_value[7:0]`
45			`i_write_value[7:0]`
46			`BINARYRADIX`
47
48
49			`state`
50			`state`
51
52
53			`clock_divider`
54			`clock_divider`
55
56
57			`clock_enable`
58			`clock_enable`
59
60
61			`clock_enable_x2`
62			`clock_enable_x2`
63
64
65			`bit_counter[3:0]`
66			`bit_counter[3:0]`
67			`HEXRADIX`
68
69
70			`bit_counter_end`
71			`bit_counter_end`
72
73
74			`delay_counter_end`
75			`delay_counter_end`
76
77
78			`byte_counter_end`
79			`byte_counter_end`
80
81
82			`sclk`
83			`sclk`
84
85
86			`write_value_reg[7:0]`
87			`write_value_reg[7:0]`
88			`BINARYRADIX`
89
90
91			`mosi`
92			`mosi`
93
94
95			`miso`
96			`miso`
97
98
99			`read_value[7:0]`
100			`read_value[7:0]`
101			`BINARYRADIX`
102
103
104			`read_value_valid`
105			`read_value_valid`
106
107
108			`ready`
109			`ready`
110
111
112			`busy`
113			`busy`
114
115
116			`ss[0:0]`
117			`ss[0:0]`
118
119

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Subversion Repositories spi_master

[/] [spi_master/] [trunk/] [hw/] [simulations/] [Testbench_SPIMaster_behav.wcfg] - Blame information for rev 2