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-- AUTHOR: MEHMET BURAK AYKENAR
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-- CREATED: 09.12.2019
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-- REVISION DATE: 09.12.2019
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--
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--------------------------------------------------------------------------------
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-- DESCRIPTION:
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-- This module implements master part of SPI communication interface and can be used to any SPI slave IC.
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-- In order to read from a slave IC, mosi_data_i input signal should be assigned to desired value and en_i signal should be high.
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-- In order to write to a slave IC, en_i input signal should be high.
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-- data_ready_o output signal has the logic high value for one clock cycle as read or/and write operation finished. miso_data_o output signal
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-- has the data read from slave IC.
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-- In order to read or/and write consecutively, en_i signal should be kept high. To end the transaction, en_i input signal should be assigned to zero
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-- when data_ready_o output signal gets high.
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--------------------------------------------------------------------------------
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-- Limitation/Assumption: In order to use this module properly, the ratio of (c_clkfreq / c_sclkFreq) should be equal to 8 or more.
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-- For higher SCLK frequencies are possible but more elaboration is needed.
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-- Notes: c_cpol and c_cpha parameters are clock polarity and clock phase, respectively.
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--------------------------------------------------------------------------------
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-- VHDL DIALECT: VHDL '93
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--
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--------------------------------------------------------------------------------
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-- PROJECT : General purpose
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-- BOARD : General purpose
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-- ENTITY : spi_master
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--------------------------------------------------------------------
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-- FILE : spi_master.vhd
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--------------------------------------------------------------------------------
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-- REVISION HISTORY:
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-- REVISION DATE AUTHOR COMMENT
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-- -------- ---------- ------------ -----------
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-- 1.0 19.12.2019 M.B.AYKENAR INITIAL REVISION
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity spi_master is
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generic (
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c_clkfreq : integer := 50_000_000;
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c_sclkfreq : integer := 1_000_000;
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c_cpol : std_logic := '0';
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c_cpha : std_logic := '0'
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);
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Port (
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clk_i : in STD_LOGIC;
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en_i : in STD_LOGIC;
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mosi_data_i : in STD_LOGIC_VECTOR (7 downto 0);
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miso_data_o : out STD_LOGIC_VECTOR (7 downto 0);
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data_ready_o : out STD_LOGIC;
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cs_o : out STD_LOGIC;
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sclk_o : out STD_LOGIC;
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mosi_o : out STD_LOGIC;
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miso_i : in STD_LOGIC
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);
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end spi_master;
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architecture Behavioral of spi_master is
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--------------------------------------------------------------------------------
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-- CONSTANTS
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constant c_edgecntrlimdiv2 : integer := c_clkfreq/(c_sclkfreq*2);
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--------------------------------------------------------------------------------
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-- INTERNAL SIGNALS
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signal write_reg : std_logic_vector (7 downto 0) := (others => '0');
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signal read_reg : std_logic_vector (7 downto 0) := (others => '0');
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signal sclk_en : std_logic := '0';
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signal sclk : std_logic := '0';
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signal sclk_prev : std_logic := '0';
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signal sclk_rise : std_logic := '0';
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signal sclk_fall : std_logic := '0';
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signal pol_phase : std_logic_vector (1 downto 0) := (others => '0');
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signal mosi_en : std_logic := '0';
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signal miso_en : std_logic := '0';
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signal once : std_logic := '0';
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signal edgecntr : integer range 0 to c_edgecntrlimdiv2 := 0;
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signal cntr : integer range 0 to 15 := 0;
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--------------------------------------------------------------------------------
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-- STATE DEFINITIONS
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type states is (S_IDLE, S_TRANSFER);
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signal state : states := S_IDLE;
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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begin
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pol_phase <= c_cpol & c_cpha;
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--------------------------------------------------------------------------------
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-- SAMPLE_EN process assigns mosi_en and miso_en internal signals to sclk_fall or sclk_rise in a combinational logic according to
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-- generic parameters of c_cpol and c_cpha via pol_phase signal.
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P_SAMPLE_EN : process (pol_phase, sclk_fall, sclk_rise) begin
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case pol_phase is
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when "00" =>
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mosi_en <= sclk_fall;
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miso_en <= sclk_rise;
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when "01" =>
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mosi_en <= sclk_rise;
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miso_en <= sclk_fall;
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when "10" =>
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mosi_en <= sclk_rise;
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miso_en <= sclk_fall;
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when "11" =>
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mosi_en <= sclk_fall;
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miso_en <= sclk_rise;
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when others =>
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end case;
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end process P_SAMPLE_EN;
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--------------------------------------------------------------------------------
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-- RISEFALL_DETECT process assigns sclk_rise and sclk_fall signals in a combinational logic.
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P_RISEFALL_DETECT : process (sclk, sclk_prev) begin
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if (sclk = '1' and sclk_prev = '0') then
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sclk_rise <= '1';
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else
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sclk_rise <= '0';
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end if;
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if (sclk = '0' and sclk_prev = '1') then
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sclk_fall <= '1';
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else
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sclk_fall <= '0';
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end if;
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end process P_RISEFALL_DETECT;
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--------------------------------------------------------------------------------
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-- In the MAIN process S_IDLE and S_TRANSFER states are implemented. state changes from S_IDLE to S_TRANSFER when en_i input
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-- signal has the logic high value. At that cycle, write_reg signal is assigned to mosi_data_i input signal. According to c_cpha generic
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-- parameter, the transaction operation changes slightly. This operational difference is well explained in the paper that can be found
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-- in Documents folder of the SPI, which is located in SVN server.
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P_MAIN : process (clk_i) begin
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if (rising_edge(clk_i)) then
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data_ready_o <= '0';
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sclk_prev <= sclk;
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case state is
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--------------------------------------------------------------------------------
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when S_IDLE =>
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cs_o <= '1';
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mosi_o <= '0';
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data_ready_o <= '0';
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sclk_en <= '0';
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cntr <= 0;
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if (c_cpol = '0') then
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sclk_o <= '0';
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else
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sclk_o <= '1';
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end if;
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if (en_i = '1') then
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state <= S_TRANSFER;
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sclk_en <= '1';
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write_reg <= mosi_data_i;
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mosi_o <= mosi_data_i(7);
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read_reg <= x"00";
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end if;
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--------------------------------------------------------------------------------
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when S_TRANSFER =>
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cs_o <= '0';
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mosi_o <= write_reg(7);
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if (c_cpha = '1') then
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if (cntr = 0) then
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sclk_o <= sclk;
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if (miso_en = '1') then
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read_reg(0) <= miso_i;
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read_reg(7 downto 1) <= read_reg(6 downto 0);
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cntr <= cntr + 1;
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once <= '1';
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end if;
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elsif (cntr = 8) then
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if (once = '1') then
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data_ready_o <= '1';
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once <= '0';
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end if;
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miso_data_o <= read_reg;
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if (mosi_en = '1') then
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if (en_i = '1') then
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write_reg <= mosi_data_i;
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mosi_o <= mosi_data_i(7);
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sclk_o <= sclk;
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cntr <= 0;
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else
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state <= S_IDLE;
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cs_o <= '1';
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end if;
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end if;
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elsif (cntr = 9) then
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if (miso_en = '1') then
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state <= S_IDLE;
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cs_o <= '1';
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end if;
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else
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sclk_o <= sclk;
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if (miso_en = '1') then
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read_reg(0) <= miso_i;
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read_reg(7 downto 1) <= read_reg(6 downto 0);
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cntr <= cntr + 1;
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end if;
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if (mosi_en = '1') then
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mosi_o <= write_reg(7);
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write_reg(7 downto 1) <= write_reg(6 downto 0);
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end if;
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end if;
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else -- c_cpha = '0'
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if (cntr = 0) then
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sclk_o <= sclk;
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if (miso_en = '1') then
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read_reg(0) <= miso_i;
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read_reg(7 downto 1) <= read_reg(6 downto 0);
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cntr <= cntr + 1;
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once <= '1';
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end if;
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elsif (cntr = 8) then
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if (once = '1') then
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data_ready_o <= '1';
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once <= '0';
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end if;
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miso_data_o <= read_reg;
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sclk_o <= sclk;
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if (mosi_en = '1') then
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if (en_i = '1') then
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write_reg <= mosi_data_i;
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mosi_o <= mosi_data_i(7);
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cntr <= 0;
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else
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cntr <= cntr + 1;
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end if;
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if (miso_en = '1') then
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state <= S_IDLE;
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cs_o <= '1';
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end if;
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end if;
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elsif (cntr = 9) then
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if (miso_en = '1') then
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state <= S_IDLE;
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cs_o <= '1';
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end if;
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else
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sclk_o <= sclk;
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if (miso_en = '1') then
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read_reg(0) <= miso_i;
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read_reg(7 downto 1) <= read_reg(6 downto 0);
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cntr <= cntr + 1;
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end if;
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if (mosi_en = '1') then
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write_reg(7 downto 1) <= write_reg(6 downto 0);
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end if;
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end if;
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end if;
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end case;
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end if;
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end process P_MAIN;
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--------------------------------------------------------------------------------
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-- In the SCLK_GEN process, internal sclk signal is generated if sclk_en signal is '1'.
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P_SCLK_GEN : process (clk_i) begin
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if (rising_edge(clk_i)) then
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if (sclk_en = '1') then
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if edgecntr = c_edgecntrlimdiv2-1 then
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sclk <= not sclk;
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edgecntr <= 0;
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else
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edgecntr <= edgecntr + 1;
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end if;
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else
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edgecntr <= 0;
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if (c_cpol = '0') then
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sclk <= '0';
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else
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sclk <= '1';
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end if;
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end if;
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end if;
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end process P_SCLK_GEN;
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end Behavioral;
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