This is a ISE 13.1 project to test the spi_master.vhd model in silicon.
2
3
The target board is a Digilent Atlys board (Spartan-6 @ 100MHz), and the circuit was tested at different SPI clock frequencies.
4
5
See the scope screenshots in the spi_master_scope_photos.zip file for each SPI frequency tested.
6
7
This circuit also includes a very robust debouncing circuit to use with multiple inputs. The model, "grp_debouncer.vhd" is also published under a LGPL license.
8
9
The files are:
10
11
spi_master.vhd vhdl model for the spi_master interface
12
grp_debouncer.vhd vhdl model for the switch debouncer
13
spi_master_atlys_top.vhd vhdl model for the toplevel block to synthesize for the Atlys
14
spi_master_atlys.xise ISE 13.1 project file
15
spi_master_atlys.ucf pin lock constraints for the Atlys board
16
spi_master_scope_photos.zip Tektronix MSO2014 screenshots for the verification tests
17
spi_master_envsettings.html synthesis env settings, with the tools setup used
18
ATLYS_01.SET Tek MSO2014 settings file with the debug pin names
19
spi_master_atlys_top_bit.zip bitgen file to program the Atlys board
20
21
22
23
If you need assistance on putting this to work, please place a thread in the OpenCores forum, and I will be glad to answer.
24
If you find a bug or a model design fault, please open a bug in the bugtracker in this project page at OpenCores.
25
26
In any case, thank you very much for testing this core.
