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<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
2 
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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<center><big><big><b>System Settings</b></big></big></center><br>
4 
<A NAME="Environment Settings"></A>
5 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
6 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
7 
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
8 
</tr>
9 
<tr bgcolor='#ffff99'>
10 
<td><b>Environment Variable</b></td>
11 
<td><b>xst</b></td>
12 
<td><b>ngdbuild</b></td>
13 
<td><b>map</b></td>
14 
<td><b>par</b></td>
15 
</tr>
16 
<tr>
17 
<td>PATHEXT</td>
18 
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
19 
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
20 
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
21 
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
22 
</tr>
23 
<tr>
24 
<td>Path</td>
25 
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
26 
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
27 
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
28 
<td>C:\Xilinx\13.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\13.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\13.1\ISE_DS\common\lib\nt;<br>C:\Windows;<br>C:\csvn\bin\;<br>C:\csvn\Python25\;<br>C:\Program Files\Common Files\Microsoft Shared\Windows Live;<br>C:\Xilinx\11.1\PlanAhead\bin;<br>C:\Xilinx\11.1\common\bin\nt;<br>C:\Xilinx\11.1\ISE\bin\nt;<br>C:\Xilinx\11.1\ISE\lib\nt;<br>C:\Windows\system32;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files\Flash Magic;<br>C:\Cadence\Orcad_9.2.3\tools\Capture;<br>C:\Cadence\Orcad_9.2.3\tools\bin;<br>C:\Cadence\Orcad_9.2.3\tools\jre\bin;<br>C:\Cadence\Orcad_9.2.3\tools\fet\bin;<br>C:\Cadence\Orcad_9.2.3\tools\specctra\bin;<br>C:\Program Files\Altium Designer Winter 09\System;<br>C:\Program Files\Microsoft SQL Server\90\Tools\binn\;<br>C:\Program Files\Windows Live\Shared;<br>C:\Program Files\QuickTime\QTSystem\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\IDM Computer Solutions\UltraEdit\</td>
29 
</tr>
30 
<tr>
31 
<td>XILINX</td>
32 
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
33 
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
34 
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
35 
<td>C:\Xilinx\13.1\ISE_DS\ISE\</td>
36 
</tr>
37 
<tr>
38 
<td>XILINX_DSP</td>
39 
<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
40 
<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
41 
<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
42 
<td>C:\Xilinx\13.1\ISE_DS\ISE</td>
43 
</tr>
44 
<tr>
45 
<td>XILINX_EDK</td>
46 
<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
47 
<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
48 
<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
49 
<td>C:\Xilinx\13.1\ISE_DS\EDK</td>
50 
</tr>
51 
<tr>
52 
<td>XILINX_PLANAHEAD</td>
53 
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
54 
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
55 
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
56 
<td>C:\Xilinx\13.1\ISE_DS\PlanAhead</td>
57 
</tr>
58 
</TABLE>
59 
<A NAME="Synthesis Property Settings"></A>
60 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
61 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
62 
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
63 
</tr>
64 
<tr bgcolor='#ffff99'>
65 
<td><b>Switch Name</b></td>
66 
<td><b>Property Name</b></td>
67 
<td><b>Value</b></td>
68 
<td><b>Default Value</b></td>
69 
</tr>
70 
<tr>
71 
<td>-ifn</td>
72 
<td>&nbsp;</td>
73 
<td>spi_master_atlys_top.prj</td>
74 
<td>&nbsp;</td>
75 
</tr>
76 
<tr>
77 
<td>-ifmt</td>
78 
<td>&nbsp;</td>
79 
<td>mixed</td>
80 
<td>Mixed</td>
81 
</tr>
82 
<tr>
83 
<td>-ofn</td>
84 
<td>&nbsp;</td>
85 
<td>spi_master_atlys_top</td>
86 
<td>&nbsp;</td>
87 
</tr>
88 
<tr>
89 
<td>-ofmt</td>
90 
<td>&nbsp;</td>
91 
<td>NGC</td>
92 
<td>NGC</td>
93 
</tr>
94 
<tr>
95 
<td>-p</td>
96 
<td>&nbsp;</td>
97 
<td>xc6slx45-2-csg324</td>
98 
<td>&nbsp;</td>
99 
</tr>
100 
<tr>
101 
<td>-top</td>
102 
<td>&nbsp;</td>
103 
<td>spi_master_atlys_top</td>
104 
<td>&nbsp;</td>
105 
</tr>
106 
<tr>
107 
<td>-opt_mode</td>
108 
<td>Optimization Goal</td>
109 
<td>Speed</td>
110 
<td>Speed</td>
111 
</tr>
112 
<tr>
113 
<td>-opt_level</td>
114 
<td>Optimization Effort</td>
115 
<td>2</td>
116 
<td>1</td>
117 
</tr>
118 
<tr>
119 
<td>-power</td>
120 
<td>Power Reduction</td>
121 
<td>NO</td>
122 
<td>No</td>
123 
</tr>
124 
<tr>
125 
<td>-iuc</td>
126 
<td>Use synthesis Constraints File</td>
127 
<td>NO</td>
128 
<td>No</td>
129 
</tr>
130 
<tr>
131 
<td>-keep_hierarchy</td>
132 
<td>Keep Hierarchy</td>
133 
<td>No</td>
134 
<td>No</td>
135 
</tr>
136 
<tr>
137 
<td>-netlist_hierarchy</td>
138 
<td>Netlist Hierarchy</td>
139 
<td>As_Optimized</td>
140 
<td>As_Optimized</td>
141 
</tr>
142 
<tr>
143 
<td>-rtlview</td>
144 
<td>Generate RTL Schematic</td>
145 
<td>Yes</td>
146 
<td>No</td>
147 
</tr>
148 
<tr>
149 
<td>-glob_opt</td>
150 
<td>Global Optimization Goal</td>
151 
<td>AllClockNets</td>
152 
<td>AllClockNets</td>
153 
</tr>
154 
<tr>
155 
<td>-read_cores</td>
156 
<td>Read Cores</td>
157 
<td>YES</td>
158 
<td>Yes</td>
159 
</tr>
160 
<tr>
161 
<td>-write_timing_constraints</td>
162 
<td>Write Timing Constraints</td>
163 
<td>NO</td>
164 
<td>No</td>
165 
</tr>
166 
<tr>
167 
<td>-cross_clock_analysis</td>
168 
<td>Cross Clock Analysis</td>
169 
<td>NO</td>
170 
<td>No</td>
171 
</tr>
172 
<tr>
173 
<td>-bus_delimiter</td>
174 
<td>Bus Delimiter</td>
175 
<td>&lt;&gt;</td>
176 
<td>&lt;&gt;</td>
177 
</tr>
178 
<tr>
179 
<td>-slice_utilization_ratio</td>
180 
<td>Slice Utilization Ratio</td>
181 
<td>100</td>
182 
<td>100</td>
183 
</tr>
184 
<tr>
185 
<td>-bram_utilization_ratio</td>
186 
<td>BRAM Utilization Ratio</td>
187 
<td>100</td>
188 
<td>100</td>
189 
</tr>
190 
<tr>
191 
<td>-dsp_utilization_ratio</td>
192 
<td>DSP Utilization Ratio</td>
193 
<td>100</td>
194 
<td>100</td>
195 
</tr>
196 
<tr>
197 
<td>-reduce_control_sets</td>
198 
<td>&nbsp;</td>
199 
<td>Auto</td>
200 
<td>Auto</td>
201 
</tr>
202 
<tr>
203 
<td>-fsm_extract</td>
204 
<td>&nbsp;</td>
205 
<td>YES</td>
206 
<td>Yes</td>
207 
</tr>
208 
<tr>
209 
<td>-fsm_encoding</td>
210 
<td>&nbsp;</td>
211 
<td>Gray</td>
212 
<td>Auto</td>
213 
</tr>
214 
<tr>
215 
<td>-safe_implementation</td>
216 
<td>&nbsp;</td>
217 
<td>No</td>
218 
<td>No</td>
219 
</tr>
220 
<tr>
221 
<td>-fsm_style</td>
222 
<td>&nbsp;</td>
223 
<td>LUT</td>
224 
<td>LUT</td>
225 
</tr>
226 
<tr>
227 
<td>-ram_extract</td>
228 
<td>&nbsp;</td>
229 
<td>No</td>
230 
<td>Yes</td>
231 
</tr>
232 
<tr>
233 
<td>-rom_extract</td>
234 
<td>&nbsp;</td>
235 
<td>No</td>
236 
<td>Yes</td>
237 
</tr>
238 
<tr>
239 
<td>-shreg_extract</td>
240 
<td>&nbsp;</td>
241 
<td>NO</td>
242 
<td>Yes</td>
243 
</tr>
244 
<tr>
245 
<td>-auto_bram_packing</td>
246 
<td>&nbsp;</td>
247 
<td>NO</td>
248 
<td>No</td>
249 
</tr>
250 
<tr>
251 
<td>-resource_sharing</td>
252 
<td>&nbsp;</td>
253 
<td>YES</td>
254 
<td>Yes</td>
255 
</tr>
256 
<tr>
257 
<td>-async_to_sync</td>
258 
<td>&nbsp;</td>
259 
<td>NO</td>
260 
<td>No</td>
261 
</tr>
262 
<tr>
263 
<td>-use_dsp48</td>
264 
<td>&nbsp;</td>
265 
<td>Auto</td>
266 
<td>Auto</td>
267 
</tr>
268 
<tr>
269 
<td>-iobuf</td>
270 
<td>&nbsp;</td>
271 
<td>YES</td>
272 
<td>Yes</td>
273 
</tr>
274 
<tr>
275 
<td>-max_fanout</td>
276 
<td>&nbsp;</td>
277 
<td>100000</td>
278 
<td>100000</td>
279 
</tr>
280 
<tr>
281 
<td>-bufg</td>
282 
<td>&nbsp;</td>
283 
<td>16</td>
284 
<td>16</td>
285 
</tr>
286 
<tr>
287 
<td>-register_duplication</td>
288 
<td>&nbsp;</td>
289 
<td>YES</td>
290 
<td>Yes</td>
291 
</tr>
292 
<tr>
293 
<td>-register_balancing</td>
294 
<td>&nbsp;</td>
295 
<td>No</td>
296 
<td>No</td>
297 
</tr>
298 
<tr>
299 
<td>-optimize_primitives</td>
300 
<td>&nbsp;</td>
301 
<td>NO</td>
302 
<td>No</td>
303 
</tr>
304 
<tr>
305 
<td>-use_clock_enable</td>
306 
<td>&nbsp;</td>
307 
<td>Auto</td>
308 
<td>Auto</td>
309 
</tr>
310 
<tr>
311 
<td>-use_sync_set</td>
312 
<td>&nbsp;</td>
313 
<td>Auto</td>
314 
<td>Auto</td>
315 
</tr>
316 
<tr>
317 
<td>-use_sync_reset</td>
318 
<td>&nbsp;</td>
319 
<td>Auto</td>
320 
<td>Auto</td>
321 
</tr>
322 
<tr>
323 
<td>-iob</td>
324 
<td>&nbsp;</td>
325 
<td>Auto</td>
326 
<td>Auto</td>
327 
</tr>
328 
<tr>
329 
<td>-equivalent_register_removal</td>
330 
<td>&nbsp;</td>
331 
<td>YES</td>
332 
<td>Yes</td>
333 
</tr>
334 
<tr>
335 
<td>-slice_utilization_ratio_maxmargin</td>
336 
<td>&nbsp;</td>
337 
<td>5</td>
338 
<td>0</td>
339 
</tr>
340 
</TABLE>
341 
<A NAME="Translation Property Settings"></A>
342 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
343 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
344 
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
345 
</tr>
346 
<tr bgcolor='#ffff99'>
347 
<td><b>Switch Name</b></td>
348 
<td><b>Property Name</b></td>
349 
<td><b>Value</b></td>
350 
<td><b>Default Value</b></td>
351 
</tr>
352 
<tr>
353 
<td>-intstyle</td>
354 
<td>&nbsp;</td>
355 
<td>ise</td>
356 
<td>None</td>
357 
</tr>
358 
<tr>
359 
<td>-dd</td>
360 
<td>&nbsp;</td>
361 
<td>_ngo</td>
362 
<td>None</td>
363 
</tr>
364 
<tr>
365 
<td>-p</td>
366 
<td>&nbsp;</td>
367 
<td>xc6slx45-csg324-2</td>
368 
<td>None</td>
369 
</tr>
370 
<tr>
371 
<td>-uc</td>
372 
<td>&nbsp;</td>
373 
<td>spi_master_atlys.ucf</td>
374 
<td>None</td>
375 
</tr>
376 
</TABLE>
377 
<A NAME="Map Property Settings"></A>
378 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
379 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
380 
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
381 
</tr>
382 
<tr bgcolor='#ffff99'>
383 
<td><b>Switch Name</b></td>
384 
<td><b>Property Name</b></td>
385 
<td><b>Value</b></td>
386 
<td><b>Default Value</b></td>
387 
</tr>
388 
<tr>
389 
<td>-ol</td>
390 
<td>Place & Route Effort Level (Overall)</td>
391 
<td>high</td>
392 
<td>high</td>
393 
</tr>
394 
<tr>
395 
<td>-xe</td>
396 
<td>Placer Extra Effort Map</td>
397 
<td>NORMAL</td>
398 
<td>&nbsp;</td>
399 
</tr>
400 
<tr>
401 
<td>-xt</td>
402 
<td>Extra Cost Tables</td>
403 
<td>0</td>
404 
<td>0</td>
405 
</tr>
406 
<tr>
407 
<td>-global_opt</td>
408 
<td>Global Optimization map</td>
409 
<td>TRUE</td>
410 
<td>FALSE</td>
411 
</tr>
412 
<tr>
413 
<td>-ir</td>
414 
<td>Use RLOC Constraints</td>
415 
<td>OFF</td>
416 
<td>OFF</td>
417 
</tr>
418 
<tr>
419 
<td>-mt</td>
420 
<td>Enable Multi-Threading</td>
421 
<td>2</td>
422 
<td>0</td>
423 
</tr>
424 
<tr>
425 
<td>-t</td>
426 
<td>Starting Placer Cost Table (1-100) Map</td>
427 
<td>1</td>
428 
<td>0</td>
429 
</tr>
430 
<tr>
431 
<td>-r</td>
432 
<td>Register Ordering</td>
433 
<td>4</td>
434 
<td>4</td>
435 
</tr>
436 
<tr>
437 
<td>-equivalent_register_removal</td>
438 
<td>Equivalent Register Removal</td>
439 
<td>TRUE</td>
440 
<td>TRUE</td>
441 
</tr>
442 
<tr>
443 
<td>-intstyle</td>
444 
<td>&nbsp;</td>
445 
<td>ise</td>
446 
<td>None</td>
447 
</tr>
448 
<tr>
449 
<td>-lc</td>
450 
<td>LUT Combining</td>
451 
<td>area</td>
452 
<td>off</td>
453 
</tr>
454 
<tr>
455 
<td>-o</td>
456 
<td>&nbsp;</td>
457 
<td>spi_master_atlys_top_map.ncd</td>
458 
<td>None</td>
459 
</tr>
460 
<tr>
461 
<td>-w</td>
462 
<td>&nbsp;</td>
463 
<td>true</td>
464 
<td>false</td>
465 
</tr>
466 
<tr>
467 
<td>-pr</td>
468 
<td>Pack I/O Registers/Latches into IOBs</td>
469 
<td>off</td>
470 
<td>off</td>
471 
</tr>
472 
<tr>
473 
<td>-p</td>
474 
<td>&nbsp;</td>
475 
<td>xc6slx45-csg324-2</td>
476 
<td>None</td>
477 
</tr>
478 
</TABLE>
479 
<A NAME="Place and Route Property Settings"></A>
480 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
481 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
482 
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
483 
</tr>
484 
<tr bgcolor='#ffff99'>
485 
<td><b>Switch Name</b></td>
486 
<td><b>Property Name</b></td>
487 
<td><b>Value</b></td>
488 
<td><b>Default Value</b></td>
489 
</tr>
490 
<tr>
491 
<td>-xe</td>
492 
<td>&nbsp;</td>
493 
<td>n</td>
494 
<td>None</td>
495 
</tr>
496 
<tr>
497 
<td>-intstyle</td>
498 
<td>&nbsp;</td>
499 
<td>ise</td>
500 
<td>&nbsp;</td>
501 
</tr>
502 
<tr>
503 
<td>-mt</td>
504 
<td>Enable Multi-Threading</td>
505 
<td>4</td>
506 
<td>off</td>
507 
</tr>
508 
<tr>
509 
<td>-ol</td>
510 
<td>Place & Route Effort Level (Overall)</td>
511 
<td>high</td>
512 
<td>std</td>
513 
</tr>
514 
<tr>
515 
<td>-w</td>
516 
<td>&nbsp;</td>
517 
<td>true</td>
518 
<td>false</td>
519 
</tr>
520 
</TABLE>
521 
<A NAME="Operating System Information"></A>
522 
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
523 
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
524 
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
525 
</tr>
526 
<tr bgcolor='#ffff99'>
527 
<td><b>Operating System Information</b></td>
528 
<td><b>xst</b></td>
529 
<td><b>ngdbuild</b></td>
530 
<td><b>map</b></td>
531 
<td><b>par</b></td>
532 
</tr>
533 
<tr>
534 
<td>CPU Architecture/Speed</td>
535 
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
536 
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
537 
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
538 
<td>Intel(R) Core(TM) i7 CPU         950  @ 3.07GHz/3066 MHz</td>
539 
</tr>
540 
<tr>
541 
<td>Host</td>
542 
<td>Develop-W7</td>
543 
<td>Develop-W7</td>
544 
<td>Develop-W7</td>
545 
<td>Develop-W7</td>
546 
</tr>
547 
<tr>
548 
<td>OS Name</td>
549 
<td>Microsoft Windows 7 , 32-bit</td>
550 
<td>Microsoft Windows 7 , 32-bit</td>
551 
<td>Microsoft Windows 7 , 32-bit</td>
552 
<td>Microsoft Windows 7 , 32-bit</td>
553 
</tr>
554 
<tr>
555 
<td>OS Release</td>
556 
<td>Service Pack 1  (build 7601)</td>
557 
<td>Service Pack 1  (build 7601)</td>
558 
<td>Service Pack 1  (build 7601)</td>
559 
<td>Service Pack 1  (build 7601)</td>
560 
</tr>
561 
</TABLE>
562 
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