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[/] [spi_slave/] [tags/] [V100/] [pcore/] [opb_spi_slave_v1_00_a/] [data/] [opb_spi_slave_v2_1_0.mpd] - Blame information for rev 35

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1 2 dkoethe
###################################################################
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##
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## Name     : opb_spi_slave
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## Desc     : Microprocessor Peripheral Description
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##          : Automatically generated by PsfUtility
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##
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###################################################################
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BEGIN opb_spi_slave
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## Peripheral Options
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OPTION IPTYPE = PERIPHERAL
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OPTION IMP_NETLIST = TRUE
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OPTION HDL = VHDL
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OPTION CORE_STATE = ACTIVE
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OPTION IP_GROUP = MICROBLAZE:PPC:USER
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## Bus Interfaces
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BUS_INTERFACE BUS = MSOPB, BUS_TYPE = MASTER_SLAVE, BUS_STD = OPB
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## Generics for VHDL or Parameters for Verilog
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PARAMETER C_BASEADDR = 0x00000000, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = BASE, PAIR = C_HIGHADDR
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PARAMETER C_HIGHADDR = 0xffffffff, DT = std_logic_vector(0 to 31), BUS = MSOPB, ADDRESS = HIGH, PAIR = C_BASEADDR
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PARAMETER C_USER_ID_CODE = 0, DT = INTEGER
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PARAMETER C_OPB_AWIDTH = 32, DT = INTEGER, BUS = MSOPB
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PARAMETER C_OPB_DWIDTH = 32, DT = INTEGER, BUS = MSOPB
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PARAMETER C_FAMILY = virtex-4, DT = STRING
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PARAMETER C_SR_WIDTH = 8, DT = INTEGER
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PARAMETER C_MSB_FIRST = true, DT = BOOLEAN
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PARAMETER C_CPOL = 0, DT = INTEGER
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PARAMETER C_PHA = 0, DT = INTEGER
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PARAMETER C_FIFO_SIZE_WIDTH = 7, DT = INTEGER
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PARAMETER C_DMA_EN = true, DT = BOOLEAN
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## Ports
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PORT OPB_ABus = OPB_ABus, DIR = I, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
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PORT OPB_BE = OPB_BE, DIR = I, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
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PORT OPB_Clk = "", DIR = I, BUS = MSOPB, SIGIS = CLK
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PORT OPB_DBus = OPB_DBus, DIR = I, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
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PORT OPB_RNW = OPB_RNW, DIR = I, BUS = MSOPB
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PORT OPB_Rst = OPB_Rst, DIR = I, BUS = MSOPB, SIGIS = RST
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PORT OPB_select = OPB_select, DIR = I, BUS = MSOPB
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PORT OPB_seqAddr = OPB_seqAddr, DIR = I, BUS = MSOPB
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PORT Sln_DBus = Sl_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
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PORT Sln_errAck = Sl_errAck, DIR = O, BUS = MSOPB
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PORT Sln_retry = Sl_retry, DIR = O, BUS = MSOPB
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PORT Sln_toutSup = Sl_toutSup, DIR = O, BUS = MSOPB
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PORT Sln_xferAck = Sl_xferAck, DIR = O, BUS = MSOPB
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PORT M_ABus = M_ABus, DIR = O, VEC = [0:(C_OPB_AWIDTH-1)], BUS = MSOPB
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PORT M_BE = M_BE, DIR = O, VEC = [0:((C_OPB_DWIDTH/8)-1)], BUS = MSOPB
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PORT M_busLock = M_busLock, DIR = O, BUS = MSOPB
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PORT M_DBus = M_DBus, DIR = O, VEC = [0:(C_OPB_DWIDTH-1)], BUS = MSOPB
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PORT M_request = M_request, DIR = O, BUS = MSOPB
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PORT M_RNW = M_RNW, DIR = O, BUS = MSOPB
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PORT M_select = M_select, DIR = O, BUS = MSOPB
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PORT M_seqAddr = M_seqAddr, DIR = O, BUS = MSOPB
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PORT MOPB_errAck = OPB_errAck, DIR = I, BUS = MSOPB
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PORT MOPB_MGrant = OPB_MGrant, DIR = I, BUS = MSOPB
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PORT MOPB_retry = OPB_retry, DIR = I, BUS = MSOPB
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PORT MOPB_timeout = OPB_timeout, DIR = I, BUS = MSOPB
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PORT MOPB_xferAck = OPB_xferAck, DIR = I, BUS = MSOPB
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PORT sclk = "", DIR = I, SIGIS = CLK
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PORT ss_n = "", DIR = I
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PORT mosi = "", DIR = I
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PORT miso = "", DIR = IO, THREE_STATE = TRUE, TRI_I = miso_I, TRI_O = miso_O, TRI_T = miso_T
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PORT miso_o = "", DIR = O
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PORT miso_i = "", DIR = I
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PORT miso_t = "", DIR = O
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PORT opb_irq = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
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END

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