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dkoethe |
\chapter{Introduction}
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This document describe a SPI Slave core designed for the Xilinx EDK. \cite{bib_xilinx_edk}
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\section{Features}
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\begin{itemize}
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\item OPB-Clock and SPI-Clock are complete independent
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\item SPI can run faster than OPB if guaranteed that no TX-FIFO Underrunn or RX-FIFO Overrunn occure.
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\item variable transfer length 2..32
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\end{itemize}
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\section{Limitations}
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\begin{itemize}
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\item designed only for Xilinx Spartan-3/Virtex-4 at the moment
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\item only Slave Operation
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\end{itemize}
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\chapter{Core configuration}
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\begin{table} [h]
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\centering
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7 |
dkoethe |
\begin{tabularx} {160mm} {|l|l|c|X|} \hline
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2 |
dkoethe |
Description & Parameter Name & Allowable Values & Default Value \\ \hline
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\multicolumn{4} {|c|} {System Parameter} \\ \hline
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Base address for OPB SPI& C\_BASEADDR & 0x00 & 0x00000000 \\ \hline
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High address for OPB SPI& C\_HIGHADDR & BASEADDR+0x3F & BASEADDR+0x3f \\ \hline
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OPB address bus width & C\_OPB\_AWIDTH & 32 & 32 \\ \hline
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OPB data bus width & C\_OPB\_DWIDTH & 32 & 32 \\ \hline
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Target FPGA Family & C\_FAMILY & spartan3,virtex4 & virtex4 \\ \hline
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\multicolumn{4} {|c|} {User Parameter} \\ \hline
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Shift register width & C\_SR\_WIDTH & 8-32 & 8 \\ \hline
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Shift MSB First & C\_MSB\_FIRST & true, false & true \\ \hline
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SPI Clock Polarity & C\_CPOL & 0,1 & 0 \\ \hline
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SPI Clock Phase & C\_CPHA & 0,1 & 0 \\ \hline
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FIFO Size Width(TX/RX)\footnotemark[1] & C\_FIFO\_DEPTH & 4-7 & 4 \\ \hline
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DMA\_EN & C\_DMA\_EN & true, false & false \\ \hline
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7 |
dkoethe |
\end{tabularx}
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2 |
dkoethe |
\caption{Generics}
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\label{tab:Generics}
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\end{table}
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\footnotetext[1]{FIFO depth is $2^{Value}$ =(16,32,64,128)}
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\chapter{IO-Ports}
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\begin{table} [h]
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\centering
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dkoethe |
\begin{tabularx} {160mm}{|l|l|l|X|} \hline
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dkoethe |
\textbf{Port} & \textbf{width} & \textbf{direction} & \textbf{Description} \\ \hline
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SPI\_SCLK & 1 & input & Serial clock input \\
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SPI\_MOSI & 1 & input & Master Out Slave in \\
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SPI\_MISO & 1 & output & Master in Slave out \\
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SPI\_SS & 1 & input & Slave select \\ \hline
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opb\_irq & 1 & output & IRQ Output \\ \hline
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7 |
dkoethe |
\end{tabularx}
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2 |
dkoethe |
\caption{external ports}
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\label{tab:externalPorts}
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\end{table}
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\chapter{Registers}
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\section{Adressmap}
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\begin{table} [!h]
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\centering
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7 |
dkoethe |
\begin{tabularx} {160mm} {|l|c|c|X|} \hline
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dkoethe |
\textbf{Name} & \textbf{Adress} & \textbf{Acess} & \textbf{Description} \\ \hline
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SPI\_CR & 0x00 & R/W & SPI Control Register \\ \hline
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SPI\_SR & 0x04 & R/W & SPI Status Register \\ \hline
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SPI\_TD & 0x08 & W & SPI Transmit Data Register \\ \hline
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SPI\_RD & 0x0C & R & SPI Receive Data Register \\ \hline
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TX\_THRESH & 0x10 & R/W & TX-Threshold Prog Full/Emty \\ \hline
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RX\_THRESH & 0x14 & R/W & RX-Threshold Prog Full/Emty \\ \hline
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TX\_DMA\_CTL & 0x18 & R/W & TX DMA Control \\ \hline
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TX\_DMA\_ADDR & 0x1C & R/W & TX DMA Base Adress Offset \\ \hline
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TX\_DMA\_NUM & 0x20 & R/W & TX DMA Number of Transfers \\ \hline
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RX\_DMA\_CTL & 0x24 & R/W & RX DMA Control \\ \hline
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RX\_DMA\_ADDR & 0x28 & R/W & RX DMA Base Adress Offset \\ \hline
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RX\_DMA\_NUM & 0x2C & R/W & RX DMA Number of Transfers \\ \hline
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DGIE & 0x40 & R/W & Device global IRQ Enable Register \\ \hline
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IPISR & 0x44 & R/W & IRQ Status Register \\ \hline
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IPIER & 0x48 & R/W & IRQ Enable Register \\ \hline
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7 |
dkoethe |
\end{tabularx}
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2 |
dkoethe |
\caption{Address-Map}
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\label{tab:registers}
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\end{table}
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\section{SPI\_CR}
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\begin{table} [!h]
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\centering
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7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1.5cm}|p{3cm}|p{1.5cm}|p{1.5cm}|X|} \hline
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2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
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31 & DGE & R/W & 0 & Device Global Enable \\
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& & & & 0: Disable \\
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& & & & 1: Enable \\ \hline
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30 & TX\_EN & R/W & 0 & Transmit Enable \\
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& & & & 0: Disable \\
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& & & & 1: Enable \\ \hline
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29 & RX\_EN & R/W & 0 & Receive Enable \\
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& & & & 0: Disable \\
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& & & & 1: Enable \\ \hline
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29 & RESET & R/W & 0 & Reset Device(self cleared) \\
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& & & & 0: Normal Operation \\
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dkoethe |
& & & & 1: Reset SPI-Core(SR/FIFO) \\ \hline
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28..0 & \multicolumn{4} {c|} {reserved} \\ \hline
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\end{tabularx}
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dkoethe |
\caption{SPI\_CR Register}
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\label{tab:SPI_CR}
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\end{table}
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\section{SPI\_SR}
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\begin{table} [!h]
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\centering
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7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
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2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
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31 & TX Prog Full & R & 0 & Prog Full Flag \\
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& & & & 1: FIFO Prog Full \\ \hline
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30 & TX Full & R & 0 & Full Flag \\
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& & & & 1: FIFO Full \\ \hline
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29 & TX Overflow & R & 0 & Overflow Flag \\
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& & & & 1: FIFO Overflow \\
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& & & & (Cleared only at Reset) \\ \hline
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28 & TX Prog Empty & R & 0 & Prog Empty Flag \\
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& & & & 1: FIFO Prog Empty \\ \hline
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27 & TX Empty & R & 0 & Full Flag \\
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& & & & 1: FIFO Empty \\ \hline
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26 & TX Underflow & R & 0 & Underflow Flag \\
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& & & & 1: FIFO Underflow \\
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& & & & (Cleared only at Reset) \\ \hline
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25 & RX Prog Full & R & 0 & Prog Full Flag \\
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& & & & 1: FIFO Prog Full \\ \hline
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24 & RX Full & R & 0 & Full Flag \\
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& & & & 1: FIFO Full \\ \hline
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23 & RX Overflow & R & 0 & Overflow Flag \\
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& & & & 1: FIFO Overflow \\
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& & & & (Cleared only at Reset) \\ \hline
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22 & RX Prog Empty & R & 0 & Prog Empty Flag \\
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& & & & 1: FIFO Prog Empty \\ \hline
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21 & RX Empty & R & 0 & Full Flag \\
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& & & & 1: FIFO Empty \\ \hline
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20 & RX Underflow & R & 0 & Underflow Flag \\
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& & & & 1: FIFO Underflow \\
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& & & & (Cleared only at Reset) \\ \hline
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19 & Chip Select & R & 0 & Chip Select Flag \\
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& & & & 0: CS\_N Low \\
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& & & & 1: CS\_N High \\ \hline
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18 & TX DMA Done & R & 0 & Transmit DMA done \\
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& & & & 0: TX DMA in progress \\
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7 |
dkoethe |
& & & & 1: TX DMA all Transfers done\\ \hline
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17 & RX DMA Done & R & 0 & Receive DMA done \\
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2 |
dkoethe |
& & & & 0: RX DMA in progress \\
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& & & & 1: RX DMA all Transfers done\\ \hline
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7 |
dkoethe |
16:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx}
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2 |
dkoethe |
\caption{SPI\_SR Register}
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\label{tab:SPI_SR}
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\end{table}
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\section{TX\_THRESH}
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\begin{table}[!h]
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\centering
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7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
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2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\
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& & & \textbf{Value} & \\ \hline
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7 |
dkoethe |
31:16 & TX\_THRESH\_PROG\_FULL & R/W & 0 & Transmit Prog Full Threshold\\
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2 |
dkoethe |
& & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline
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7 |
dkoethe |
15:0 & TX\_THRESH\_PROG\_EMPTY & R/W & 0 & Transmit Prog Empty Threshold\\
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2 |
dkoethe |
& & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline
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7 |
dkoethe |
\end{tabularx}
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2 |
dkoethe |
\caption{TX\_THRESH Register}
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\label{tab:TX_THRESH}
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\end{table}
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| 175 |
7 |
dkoethe |
This Register sets the Almost Full and Empty Flag Thresholds for Transmit FIFO. IF the DMA-Engine is used, the TX\_THRESH\_PROG\_EMPTY is used to trigger the DMA-Transfer. If Transmit FIFO is Almost Empty the Engine fills the FIFO with 16 Words(4..32bit). If the OPB-Bus is at medium or full load, increase Almost Empty Threshold to ensure there are ''some bytes reserve'' in Fifo until the DMA-Engine has access to the bus and can start transfer. Under light load condition a value of 4 should sufficient.
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2 |
dkoethe |
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7 |
dkoethe |
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| 178 |
2 |
dkoethe |
\section{RX\_THRESH}
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| 179 |
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\begin{table}[!h]
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| 180 |
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\centering
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| 181 |
7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
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| 182 |
2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset} & \textbf{Description} \\
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& & & \textbf{Value} & \\ \hline
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7 |
dkoethe |
31:16 & RX\_THRESH\_PROG\_FULL & R/W & 0 & Receive Prog Full Threshold \\
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2 |
dkoethe |
& & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline
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| 186 |
7 |
dkoethe |
15:0 & RX\_THRESH\_PROG\_EMPTY & R/W & 0 & Receive Prog Empty Threshold\\
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& & & & [1..$2^{C\_FIFO\_DEPTH}-2$] \\ \hline \end{tabularx}
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2 |
dkoethe |
\caption{RX\_THRESH Register}
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\label{tab:RX_THRESH}
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\end{table}
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| 192 |
7 |
dkoethe |
This Register sets the Almost Full and Empty Flag Thresholds for Receive FIFO. IF the DMA-Engine is used, the RX\_THRESH\_PROG\_FULL is used to trigger the DMA-Transfer. Normally set this Threshold to the block size of 16. If the OPB-Bus is at medium or full load, increase the FIFO Size(C\_FIFO\_WIDTH) to ensure there are 'some bytes free'' in FIFO until overflow occurs.
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2 |
dkoethe |
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| 194 |
7 |
dkoethe |
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| 195 |
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\section{TX\_DMA\_CTL}
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| 196 |
2 |
dkoethe |
\begin{table} [!h]
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| 197 |
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\centering
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| 198 |
7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
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| 199 |
2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
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| 200 |
7 |
dkoethe |
31 & TX\_DMA\_EN & R/W & 0 & Transmit DMA Enable \\
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| 201 |
2 |
dkoethe |
& & & & 0: Disable \\
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| 202 |
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& & & & 1: Enable \\ \hline
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| 203 |
7 |
dkoethe |
29:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx}
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\caption{TX\_DMA\_CTL Register}
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\label{tab:tx_dma_ctl}
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| 206 |
2 |
dkoethe |
\end{table}
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7 |
dkoethe |
This Register is only available if C\_DMA\_EN is set.
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Set the Bit TX\_DMA\_EN to 1 to enable the Transmit DMA Engine. With Engine Start the Register TX\_DMA\_ADDR and TX\_DMA\_NUM are copied to internal register. Do not change this Registers if DMA Enable set.
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2 |
dkoethe |
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| 210 |
7 |
dkoethe |
\section{TX\_DMA\_ADDR}
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| 211 |
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\begin{table} [!h]
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| 212 |
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\centering
|
| 213 |
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\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 214 |
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\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
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| 215 |
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31:0 & TX\_DMA\_Adr & R/W & 0 & Transmit DMA Base Adress \\ \hline
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| 216 |
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\end{tabularx}
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| 217 |
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\caption{TX\_DMA\_ADDR Register}
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| 218 |
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\label{tab:tx_dma_addr}
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| 219 |
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\end{table}
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| 220 |
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| 221 |
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This Register is only available if C\_DMA\_EN is set. With this Register the Base-Adress of the TX-DMA is set. The Adress must 4 Byte aligned. Remark: For this memory area the Data-Chache of the Microblaze can be enabled, because the Cache is a Write-True type. Using a controller with write-back cache only the first write will written in memory, the second only in the internal cache.
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| 222 |
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| 223 |
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\section{TX\_DMA\_NUM}
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| 224 |
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\begin{table} [!h]
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| 225 |
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\centering
|
| 226 |
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\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 227 |
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\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
|
| 228 |
11 |
dkoethe |
31:8 & TX\_DMA\_LEN & R/W & 0 & TX DMA Number of Block Transfers \\ \hline
|
| 229 |
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7:0 & \multicolumn{4} {c|} {reserved} \\ \hline
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| 230 |
7 |
dkoethe |
\end{tabularx}
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| 231 |
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\caption{TX\_DMA\_NUM Register}
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| 232 |
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\label{tab:tx_dma_len}
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| 233 |
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\end{table}
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| 234 |
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This Register is only available if C\_DMA\_EN is set. The Register set the Number of Blocktransfers. If all transfers done, the IRQ TX DMA Done asserted. The block size of the DMA is 16. A system configured with C\_SR\_WIDTH = 8 transfers 16 Bytes, if C\_SR\_WIDTH=32 64 Bytes are written to or read from the memory in one DMA-Cycle.
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| 235 |
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| 236 |
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\section{RX\_DMA\_CTL}
|
| 237 |
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\begin{table} [!h]
|
| 238 |
|
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\centering
|
| 239 |
|
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\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 240 |
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\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
|
| 241 |
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31 & RX\_DMA\_EN & R/W & 0 & Transmit DMA Enable \\
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| 242 |
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& & & & 0: Disable \\
|
| 243 |
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& & & & 1: Enable \\ \hline
|
| 244 |
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29:0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx}
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| 245 |
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\caption{RX\_DMA\_CTL Register}
|
| 246 |
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\label{tab:RX_dma_ctl}
|
| 247 |
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\end{table}
|
| 248 |
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|
| 249 |
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This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_CTL for Description.
|
| 250 |
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|
| 251 |
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|
| 252 |
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\section{RX\_DMA\_ADDR}
|
| 253 |
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\begin{table} [!h]
|
| 254 |
|
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\centering
|
| 255 |
|
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\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 256 |
|
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\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
|
| 257 |
|
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31:0 & RX\_DMA\_Adr & R/W & 0 & Transmit DMA Base Adress \\ \hline
|
| 258 |
|
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\end{tabularx}
|
| 259 |
|
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\caption{RX\_DMA\_ADDR Register}
|
| 260 |
|
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\label{tab:RX_dma_addr}
|
| 261 |
|
|
\end{table}
|
| 262 |
|
|
|
| 263 |
|
|
This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_ADDR for Description.
|
| 264 |
|
|
\newline
|
| 265 |
|
|
\fbox{\parbox{160mm} {Remark: Check RX\_DMA\_ADDR that is set to the right memory section. If wrong set, program-Code or date overwritten with SPI-Data!}}
|
| 266 |
|
|
|
| 267 |
|
|
\section{RX\_DMA\_NUM}
|
| 268 |
|
|
\begin{table} [!h]
|
| 269 |
|
|
\centering
|
| 270 |
|
|
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 271 |
|
|
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
|
| 272 |
11 |
dkoethe |
31:8 & RX\_DMA\_LEN & R/W & 0 & RX DMA Number of Block Transfers \\ \hline
|
| 273 |
|
|
7:0 & \multicolumn{4} {c|} {reserved} \\ \hline
|
| 274 |
7 |
dkoethe |
\end{tabularx}
|
| 275 |
|
|
\caption{RX\_DMA\_NUM Register}
|
| 276 |
|
|
\label{tab:RX_dma_len}
|
| 277 |
|
|
\end{table}
|
| 278 |
|
|
|
| 279 |
|
|
This Register is only available if C\_DMA\_EN is set. See Register TX\_DMA\_NUM for Description.
|
| 280 |
|
|
|
| 281 |
2 |
dkoethe |
\section{IPISR}
|
| 282 |
|
|
\begin{table} [!h]
|
| 283 |
|
|
\centering
|
| 284 |
7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 285 |
2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
|
| 286 |
|
|
31 & TX\_Prog\_Empty & R/ToW\footnotemark[1] & 0 & IRQ Prog Empty Flag \\ \hline
|
| 287 |
|
|
29 & TX\_Empty & R/ToW & 0 & IRQ Full Flag \\ \hline
|
| 288 |
|
|
28 & RX\_Prog\_Full& R/ToW & 0 & IRQ Prog Full Flag \\ \hline
|
| 289 |
|
|
27 & RX\_Full & R/ToW & 0 & IRQ Full Flag \\ \hline
|
| 290 |
|
|
26 & SS\_FALL & R/ToW & 0 & IRQ SS FALL Flag \\ \hline
|
| 291 |
|
|
25 & SS\_RISE & R/ToW & 0 & IRQ SS RISE Flag \\ \hline
|
| 292 |
7 |
dkoethe |
24..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx}
|
| 293 |
2 |
dkoethe |
\caption{IPISR Register}
|
| 294 |
|
|
\label{tab:IPISR}
|
| 295 |
|
|
\end{table}
|
| 296 |
|
|
|
| 297 |
|
|
\footnotetext[1]{Read and ToggleOnWrite (writing 1 clears the bit)}
|
| 298 |
|
|
|
| 299 |
|
|
\section{IPISE}
|
| 300 |
|
|
\begin{table} [!h]
|
| 301 |
|
|
\centering
|
| 302 |
7 |
dkoethe |
\begin{tabularx} {160mm}{|p{1cm}|p{5cm}|p{1.5cm}|p{1cm}|X|} \hline
|
| 303 |
2 |
dkoethe |
\textbf{Bit} & \textbf{Name} & \textbf{Acess} & \textbf{Reset Value} & \textbf{Description} \\ \hline
|
| 304 |
|
|
31 & TX\_Prog\_Empty & R/W & 0 & IRQ Prog Empty Enable \\ \hline
|
| 305 |
|
|
29 & TX\_Empty & R/W & 0 & IRQ Full Enable \\ \hline
|
| 306 |
|
|
28 & RX\_Prog\_Full & R/W & 0 & IRQ Prog Full Enable \\ \hline
|
| 307 |
|
|
27 & RX\_Full & R/W & 0 & IRQ Full Enable \\ \hline
|
| 308 |
|
|
26 & SS\_FALL & R/W & 0 & IRQ SS FALL Enable \\ \hline
|
| 309 |
|
|
25 & SS\_RISE & R/W & 0 & IRQ SS RISE Enable \\ \hline
|
| 310 |
|
|
24 & TX\_DMA\_DONE & R/W & 0 & IRQ TX Transfer done Enable\\ \hline
|
| 311 |
7 |
dkoethe |
23 & TX\_DMA\_DONE & R/W & 0 & IRQ RX Transfer done Enable\\ \hline
|
| 312 |
|
|
22..0 & \multicolumn{4} {c|} {reserved} \\ \hline \end{tabularx}
|
| 313 |
2 |
dkoethe |
\caption{IPISE Register}
|
| 314 |
|
|
\label{tab:IPISE}
|
| 315 |
|
|
\end{table}
|
| 316 |
|
|
|
| 317 |
|
|
|
| 318 |
|
|
\chapter{System Integration}
|
| 319 |
|
|
To integrate this IP-Core in your System, unzip the opb\_spi\_slave.zip to your project-directory. Then Rescan the user repository with \textit{Project $\rightarrow$ Rescan User Repositories}. This will take some seconds. After this you find the core in the \textit{IP Catalog $\rightarrow$ Project Repository}.
|
| 320 |
|
|
|
| 321 |
|
|
\section{MPD-File}
|
| 322 |
|
|
\begin{verbatim}
|
| 323 |
|
|
BEGIN opb_spi_slave
|
| 324 |
|
|
PARAMETER INSTANCE = opb_spi_slave_0
|
| 325 |
|
|
PARAMETER HW_VER = 1.00.a
|
| 326 |
|
|
PARAMETER C_BASEADDR = 0x7d600000
|
| 327 |
|
|
PARAMETER C_HIGHADDR = 0x7d60ffff
|
| 328 |
|
|
BUS_INTERFACE MSOPB = mb_opb
|
| 329 |
|
|
PORT sclk = opb_spi_slave_0_sclk
|
| 330 |
|
|
PORT ss_n = opb_spi_slave_0_ss_n
|
| 331 |
|
|
PORT mosi = opb_spi_slave_0_mosi
|
| 332 |
|
|
PORT miso = opb_spi_slave_0_miso
|
| 333 |
|
|
PORT opb_irq = opb_spi_slave_0_opb_irq
|
| 334 |
|
|
END
|
| 335 |
|
|
\end{verbatim}
|
| 336 |
|
|
|
| 337 |
|
|
\section{UCF-File}
|
| 338 |
|
|
\begin{verbatim}
|
| 339 |
|
|
# assign I/O Pins
|
| 340 |
|
|
NET opb_spi_slave_0_sclk_pin LOC= AA24; # must CC capable IO in virtex-4
|
| 341 |
|
|
NET opb_spi_slave_0_ss_n_pin LOC= V20;
|
| 342 |
|
|
NET opb_spi_slave_0_mosi_pin LOC= AC25;
|
| 343 |
|
|
NET opb_spi_slave_0_miso_pin LOC= AC24;
|
| 344 |
|
|
NET opb_spi_slave_0_miso_pin SLEW = FAST;
|
| 345 |
|
|
|
| 346 |
|
|
#### Module OPB_SPI_Slave constraints
|
| 347 |
|
|
Net opb_spi_slave_0_sclk_pin TNM_NET = spi_clk;
|
| 348 |
|
|
TIMESPEC TS_spi_clk = PERIOD spi_clk 40 ns;
|
| 349 |
|
|
|
| 350 |
|
|
NET "opb_spi_slave_0_mosi_pin" TNM = "spi_in";
|
| 351 |
|
|
#NET "opb_spi_slave_0_cs_n_pin" TNM = "spi_in";
|
| 352 |
|
|
TIMEGRP "spi_in" OFFSET = IN 5 ns VALID 10 ns BEFORE "opb_spi_slave_0_sclk_pin" HIGH ;
|
| 353 |
|
|
|
| 354 |
|
|
NET "opb_spi_slave_0_miso_pin" TNM = "spi_out";
|
| 355 |
|
|
TIMEGRP "spi_out" OFFSET = OUT 14 ns AFTER "opb_spi_slave_0_sclk_pin" LOW ;
|
| 356 |
|
|
\end{verbatim}
|
| 357 |
|
|
|
| 358 |
|
|
\section{Register Header}
|
| 359 |
|
|
|
| 360 |
|
|
\verbatiminput{opb_spi_slave.h}
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
\chapter{Operations}
|
| 364 |
|
|
|
| 365 |
7 |
dkoethe |
|
| 366 |
2 |
dkoethe |
\chapter{Architecture}
|
| 367 |
|
|
|
| 368 |
|
|
\begin{figure}[h]
|
| 369 |
|
|
\centering
|
| 370 |
|
|
\includegraphics[width=1.00\textwidth]{Grafik/block_diagramm}
|
| 371 |
|
|
\caption{Blockdiagramm}
|
| 372 |
|
|
\label{fig:blockdiagramm}
|
| 373 |
|
|
\end{figure}
|
| 374 |
|
|
|
