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[/] [spi_slave/] [trunk/] [pcore/] [opb_spi_slave_v1_00_a/] [hdl/] [vhdl/] [bin2gray.vhd] - Blame information for rev 35

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Line No. Rev Author Line
1 2 dkoethe
-------------------------------------------------------------------------------
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--* 
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--* @short convert binary input vector to gray
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--* 
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--* @generic width              with of input vector
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--*
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--*    @author: Daniel Köthe
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--*   @version: 1.0
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--* @date:      2007-11-11
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--/
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_arith.all;
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entity bin2gray is
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  generic (
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    width : integer := 4);
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  port (
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    in_bin   : in  std_logic_vector(width-1 downto 0);
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    out_gray : out std_logic_vector(width-1 downto 0));
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end bin2gray;
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architecture behavior of bin2gray is
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begin  -- behavior
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  -- Sequence: 0,1,3,2,6,7,5,4,C,D,F,E,A,B,9,8
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  --* convert binary input vector to gray
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  bin2gray_proc : process(in_bin)
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  begin
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    out_gray(width-1) <= in_bin(width-1);
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    -- out_gray(3) <= in_bin(3);
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    for i in 1 to width-1 loop
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      out_gray(width-1-i) <= in_bin(width-i) xor in_bin(width-1-i);
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    end loop;  -- i
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  end process bin2gray_proc;
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  -- i=1 out_gray(2) <= in_bin(3) xor in_bin(2);
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  -- i=2 out_gray(1) <= in_bin(2) xor in_bin(1);
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  -- i=3 out_gray(0) <= in_bin(1) xor in_bin(0);  
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end behavior;

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