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[/] [spi_slave/] [trunk/] [pcore/] [opb_spi_slave_v1_00_a/] [hdl/] [vhdl/] [opb_spi_slave.vhd] - Blame information for rev 23

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-------------------------------------------------------------------------------
--* 
--* @short Top entity of the project opi_spi_slave
--* 
--* @generic C_FAMILY virtex-4 and generic supported
--*    @author: Daniel K�the
--*   @version: 1.1
--* @date: 2007-11-19
--/
-- Version 1.1
-- Bugfix
-- IRQ-Flag RX_Overflow shows prog_empty insteed rx_overflow
-- opb_irq_flg(5) <= opb_fifo_flg(9); to opb_irq_flg(5) <= opb_fifo_flg(8); 
 
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
 
library UNISIM;
use UNISIM.vcomponents.all;
 
library work;
use work.opb_spi_slave_pack.all;
 
 
entity opb_spi_slave is
 
  generic (
    C_BASEADDR     : std_logic_vector(0 to 31) := X"00000000";
    C_HIGHADDR     : std_logic_vector(0 to 31) := X"FFFFFFFF";
    C_USER_ID_CODE : integer                   := 0;
    C_OPB_AWIDTH   : integer                   := 32;
    C_OPB_DWIDTH   : integer                   := 32;
 
    C_FAMILY          : string               := "virtex4";
    -- user ports
    C_SR_WIDTH        : integer              := 8;
    C_MSB_FIRST       : boolean              := true;
    C_CPOL            : integer range 0 to 1 := 0;
    C_PHA             : integer range 0 to 1 := 0;
    C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5;  -- depth 32
    C_DMA_EN          : boolean              := false;
    C_CRC_EN          : boolean              := false);
 
  port (
    -- OPB signals (Slave Side)
    OPB_ABus    : in  std_logic_vector(0 to C_OPB_AWIDTH-1);
    OPB_BE      : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);
    OPB_Clk     : in  std_logic;
    OPB_DBus    : in  std_logic_vector(0 to C_OPB_DWIDTH-1);
    OPB_RNW     : in  std_logic;
    OPB_Rst     : in  std_logic;
    OPB_select  : in  std_logic;
    OPB_seqAddr : in  std_logic;
    Sln_DBus    : out std_logic_vector(0 to C_OPB_DWIDTH-1);
    Sln_errAck  : out std_logic;
    Sln_retry   : out std_logic;
    Sln_toutSup : out std_logic;
    Sln_xferAck : out std_logic;
 
    -- OPB signals (Master Side)
    -- Arbitration
    M_request    : out std_logic;
    MOPB_MGrant  : in  std_logic;
    M_busLock    : out std_logic;
    -- 
    M_ABus       : out std_logic_vector(0 to C_OPB_AWIDTH-1);
    M_BE         : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
    M_DBus       : out std_logic_vector(0 to C_OPB_DWIDTH-1);
    M_RNW        : out std_logic;
    M_select     : out std_logic;
    M_seqAddr    : out std_logic;
    MOPB_errAck  : in  std_logic;
    MOPB_retry   : in  std_logic;
    MOPB_timeout : in  std_logic;
    MOPB_xferAck : in  std_logic;
    -- spi ports
    sclk         : in  std_logic;
    ss_n         : in  std_logic;
    mosi         : in  std_logic;
    miso_o       : out std_logic;
    miso_i       : in  std_logic;
    miso_t       : out std_logic;
    -- irq output
    opb_irq      : out std_logic);
 
end opb_spi_slave;
 
architecture behavior of opb_spi_slave is
 
  component opb_if
    generic (
      C_BASEADDR        : std_logic_vector(0 to 31);
      C_HIGHADDR        : std_logic_vector(0 to 31);
      C_USER_ID_CODE    : integer;
      C_OPB_AWIDTH      : integer;
      C_OPB_DWIDTH      : integer;
      C_FAMILY          : string;
      C_SR_WIDTH        : integer;
      C_FIFO_SIZE_WIDTH : integer;
      C_DMA_EN          : boolean;
      C_CRC_EN          : boolean);
    port (
      OPB_ABus         : in  std_logic_vector(0 to C_OPB_AWIDTH-1);
      OPB_BE           : in  std_logic_vector(0 to C_OPB_DWIDTH/8-1);
      OPB_Clk          : in  std_logic;
      OPB_DBus         : in  std_logic_vector(0 to C_OPB_DWIDTH-1);
      OPB_RNW          : in  std_logic;
      OPB_Rst          : in  std_logic;
      OPB_select       : in  std_logic;
      OPB_seqAddr      : in  std_logic;
      Sln_DBus         : out std_logic_vector(0 to C_OPB_DWIDTH-1);
      Sln_errAck       : out std_logic;
      Sln_retry        : out std_logic;
      Sln_toutSup      : out std_logic;
      Sln_xferAck      : out std_logic;
      opb_s_tx_en      : out std_logic;
      opb_s_tx_data    : out std_logic_vector(C_SR_WIDTH-1 downto 0);
      opb_s_rx_en      : out std_logic;
      opb_s_rx_data    : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      opb_ctl_reg      : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
      tx_thresh        : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
      rx_thresh        : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
      opb_fifo_flg     : in  std_logic_vector(C_NUM_FLG-1 downto 0);
      opb_dgie         : out std_logic;
      opb_ier          : out std_logic_vector(C_NUM_INT-1 downto 0);
      opb_isr          : in  std_logic_vector(C_NUM_INT-1 downto 0);
      opb_isr_clr      : out std_logic_vector(C_NUM_INT-1 downto 0);
      opb_tx_dma_addr  : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
      opb_tx_dma_ctl   : out std_logic_vector(0 downto 0);
      opb_tx_dma_num   : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
      opb_rx_dma_addr  : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);
      opb_rx_dma_ctl   : out std_logic_vector(0 downto 0);
      opb_rx_dma_num   : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
      opb_rx_crc_value : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      opb_tx_crc_value : in  std_logic_vector(C_SR_WIDTH-1 downto 0));
 
  end component;
 
 
  component opb_m_if
    generic (
      C_BASEADDR        : std_logic_vector(0 to 31);
      C_HIGHADDR        : std_logic_vector(0 to 31);
      C_USER_ID_CODE    : integer;
      C_OPB_AWIDTH      : integer;
      C_OPB_DWIDTH      : integer;
      C_FAMILY          : string;
      C_SR_WIDTH        : integer;
      C_MSB_FIRST       : boolean;
      C_CPOL            : integer range 0 to 1;
      C_PHA             : integer range 0 to 1;
      C_FIFO_SIZE_WIDTH : integer range 4 to 7);
    port (
      OPB_Clk          : in  std_logic;
      OPB_Rst          : in  std_logic;
      OPB_DBus         : in  std_logic_vector(0 to C_OPB_DWIDTH-1);
      M_request        : out std_logic;
      MOPB_MGrant      : in  std_logic;
      M_busLock        : out std_logic;
      M_ABus           : out std_logic_vector(0 to C_OPB_AWIDTH-1);
      M_BE             : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);
      M_DBus           : out std_logic_vector(0 to C_OPB_DWIDTH-1);
      M_RNW            : out std_logic;
      M_select         : out std_logic;
      M_seqAddr        : out std_logic;
      MOPB_errAck      : in  std_logic;
      MOPB_retry       : in  std_logic;
      MOPB_timeout     : in  std_logic;
      MOPB_xferAck     : in  std_logic;
      opb_m_tx_req     : in  std_logic;
      opb_m_tx_en      : out std_logic;
      opb_m_tx_data    : out std_logic_vector(C_SR_WIDTH-1 downto 0);
      opb_tx_dma_ctl   : in  std_logic_vector(0 downto 0);
      opb_tx_dma_addr  : in  std_logic_vector(C_OPB_DWIDTH-1 downto 0);
      opb_tx_dma_num   : in  std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
      opb_tx_dma_done  : out std_logic;
      opb_m_rx_req     : in  std_logic;
      opb_m_rx_en      : out std_logic;
      opb_m_rx_data    : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      opb_rx_dma_ctl   : in  std_logic_vector(0 downto 0);
      opb_rx_dma_addr  : in  std_logic_vector(C_OPB_DWIDTH-1 downto 0);
      opb_rx_dma_num   : in  std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
      opb_rx_dma_done  : out std_logic;
      opb_abort_flg    : out std_logic;
      opb_m_last_block : out std_logic);
  end component;
 
  component shift_register
    generic (
      C_SR_WIDTH  : integer;
      C_MSB_FIRST : boolean;
      C_CPOL      : integer range 0 to 1;
      C_PHA       : integer range 0 to 1);
    port (
      rst         : in  std_logic;
      opb_ctl_reg : in  std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
      sclk        : in  std_logic;
      ss_n        : in  std_logic;
      mosi        : in  std_logic;
      miso_o      : out std_logic;
      miso_i      : in  std_logic;
      miso_t      : out std_logic;
      sr_tx_clk   : out std_logic;
      sr_tx_en    : out std_logic;
      sr_tx_data  : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      sr_rx_clk   : out std_logic;
      sr_rx_en    : out std_logic;
      sr_rx_data  : out std_logic_vector(C_SR_WIDTH-1 downto 0));
  end component;
 
  component fifo
    generic (
      C_FIFO_WIDTH      : integer;
      C_FIFO_SIZE_WIDTH : integer;
      C_SYNC_TO         : string);
    port (
      rst               : in  std_logic;
      wr_clk            : in  std_logic;
      wr_en             : in  std_logic;
      din               : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      rd_clk            : in  std_logic;
      rd_en             : in  std_logic;
      dout              : out std_logic_vector(C_SR_WIDTH-1 downto 0);
      empty             : out std_logic;
      full              : out std_logic;
      overflow          : out std_logic;
      underflow         : out std_logic;
      prog_empty_thresh : in  std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0);
      prog_full_thresh  : in  std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0);
      prog_empty        : out std_logic;
      prog_full         : out std_logic);
  end component;
 
  component irq_ctl
    generic (
      C_ACTIVE_EDGE : std_logic);
    port (
      rst          : in  std_logic;
      clk          : in  std_logic;
      opb_fifo_flg : in  std_logic;
      opb_ier      : in  std_logic;
      opb_isr      : out std_logic;
      opb_isr_clr  : in  std_logic);
  end component;
 
  component crc_core
    generic (
      C_SR_WIDTH : integer);
    port (
      rst              : in  std_logic;
      opb_clk          : in  std_logic;
      crc_en           : in  std_logic;
      crc_clr          : in  std_logic;
      opb_m_last_block : in  std_logic;
      fifo_rx_en       : in  std_logic;
      fifo_rx_data     : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0);
      fifo_tx_en       : in  std_logic;
      fifo_tx_data     : in  std_logic_vector(C_SR_WIDTH-1 downto 0);
      tx_crc_insert    : out std_logic;
      opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0));
  end component;
 
-- opb_if
  signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);
 
  signal opb_s_tx_en   : std_logic;
  signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
  signal opb_s_rx_en   : std_logic;
  signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
  signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);
 
  signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
  signal opb_tx_dma_ctl  : std_logic_vector(0 downto 0);
  signal opb_tx_dma_num  : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
  signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0);
  signal opb_rx_dma_ctl  : std_logic_vector(0 downto 0);
  signal opb_rx_dma_num  : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);
 
  signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);
  signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  -- opb_m_if
  signal opb_m_tx_en      : std_logic;
  signal opb_m_tx_data    : std_logic_vector(C_SR_WIDTH-1 downto 0);
  signal opb_m_rx_en      : std_logic;
  signal opb_m_rx_data    : std_logic_vector(C_SR_WIDTH-1 downto 0);
  signal opb_abort_flg    : std_logic;
  signal opb_m_last_block : std_logic;
 
-- shift_register
  signal sr_tx_clk  : std_logic;
  signal sr_tx_en   : std_logic;
  signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
  signal sr_rx_clk  : std_logic;
  signal sr_rx_en   : std_logic;
  signal sr_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  signal sclk_ibuf : std_logic;
  signal sclk_bufr : std_logic;
 
  signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0);
  signal opb_irq_flg  : std_logic_vector(C_NUM_INT-1 downto 0) := (others => '0');
  signal rst          : std_logic;
 
 
  signal opb_dgie    : std_logic;
  signal opb_ier     : std_logic_vector(C_NUM_INT-1 downto 0);
  signal opb_isr     : std_logic_vector(C_NUM_INT-1 downto 0);
  signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0);
 
  -- opb_spi_slave
  signal fifo_tx_en   : std_logic;
  signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
  signal fifo_rx_en   : std_logic;
  signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);
 
  -- rx crc_core
  signal crc_clr       : std_logic;
  signal crc_en        : std_logic;
  signal tx_crc_insert : std_logic;
 
begin  -- behavior
 
  --* 
  virtex4_slk_buf : if C_FAMILY = "virtex4" generate
    --* If C_FAMILY=Virtex-4 use "IBUF"
    IBUF_1 : IBUF
      port map (
        I => sclk,
        O => sclk_ibuf);
 
--* If C_FAMILY=Virtex-4 use "BUFR"
    BUFR_1 : BUFR
      generic map (
        BUFR_DIVIDE => "BYPASS",
        SIM_DEVICE  => "VIRTEX4")
      port map (
        O   => sclk_bufr,
        CE  => '0',
        CLR => '0',
        I   => sclk_ibuf);
  end generate virtex4_slk_buf;
 
  generic_sclk_buf : if C_FAMILY /= "virtex4" generate
    sclk_bufr <= sclk;
  end generate generic_sclk_buf;
 
  --* OPB-Slave Interface(Register-Interface)
  opb_if_2 : opb_if
    generic map (
      C_BASEADDR        => C_BASEADDR,
      C_HIGHADDR        => C_HIGHADDR,
      C_USER_ID_CODE    => C_USER_ID_CODE,
      C_OPB_AWIDTH      => C_OPB_AWIDTH,
      C_OPB_DWIDTH      => C_OPB_DWIDTH,
      C_FAMILY          => C_FAMILY,
      C_SR_WIDTH        => C_SR_WIDTH,
      C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,
      C_DMA_EN          => C_DMA_EN,
      C_CRC_EN          => C_CRC_EN)
    port map (
      OPB_ABus         => OPB_ABus,
      OPB_BE           => OPB_BE,
      OPB_Clk          => OPB_Clk,
      OPB_DBus         => OPB_DBus,
      OPB_RNW          => OPB_RNW,
      OPB_Rst          => OPB_Rst,
      OPB_select       => OPB_select,
      OPB_seqAddr      => OPB_seqAddr,
      Sln_DBus         => Sln_DBus,
      Sln_errAck       => Sln_errAck,
      Sln_retry        => Sln_retry,
      Sln_toutSup      => Sln_toutSup,
      Sln_xferAck      => Sln_xferAck,
      opb_s_tx_en      => opb_s_tx_en,
      opb_s_tx_data    => opb_s_tx_data,
      opb_s_rx_en      => opb_s_rx_en,
      opb_s_rx_data    => opb_s_rx_data,
      opb_ctl_reg      => opb_ctl_reg,
      tx_thresh        => tx_thresh,
      rx_thresh        => rx_thresh,
      opb_fifo_flg     => opb_fifo_flg,
      opb_dgie         => opb_dgie,
      opb_ier          => opb_ier,
      opb_isr          => opb_isr,
      opb_isr_clr      => opb_isr_clr,
      opb_tx_dma_addr  => opb_tx_dma_addr,
      opb_tx_dma_ctl   => opb_tx_dma_ctl,
      opb_tx_dma_num   => opb_tx_dma_num,
      opb_rx_dma_addr  => opb_rx_dma_addr,
      opb_rx_dma_ctl   => opb_rx_dma_ctl,
      opb_rx_dma_num   => opb_rx_dma_num,
      opb_rx_crc_value => opb_rx_crc_value,
      opb_tx_crc_value => opb_tx_crc_value);
 
  --* OPB-Master-Interface
  --*
  --* (DMA Read/Write Transfers to TX/RX-FIFO)
 
  dma_enable : if (C_DMA_EN = true) generate
    opb_m_if_1 : opb_m_if
      generic map (
        C_BASEADDR        => C_BASEADDR,
        C_HIGHADDR        => C_HIGHADDR,
        C_USER_ID_CODE    => C_USER_ID_CODE,
        C_OPB_AWIDTH      => C_OPB_AWIDTH,
        C_OPB_DWIDTH      => C_OPB_DWIDTH,
        C_FAMILY          => C_FAMILY,
        C_SR_WIDTH        => C_SR_WIDTH,
        C_MSB_FIRST       => C_MSB_FIRST,
        C_CPOL            => C_CPOL,
        C_PHA             => C_PHA,
        C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH)
      port map (
        OPB_Clk          => OPB_Clk,
        OPB_Rst          => OPB_Rst,
        OPB_DBus         => OPB_DBus,
        M_request        => M_request,
        MOPB_MGrant      => MOPB_MGrant,
        M_busLock        => M_busLock,
        M_ABus           => M_ABus,
        M_BE             => M_BE,
        M_DBus           => M_DBus,
        M_RNW            => M_RNW,
        M_select         => M_select,
        M_seqAddr        => M_seqAddr,
        MOPB_errAck      => MOPB_errAck,
        MOPB_retry       => MOPB_retry,
        MOPB_timeout     => MOPB_timeout,
        MOPB_xferAck     => MOPB_xferAck,
        opb_m_tx_req     => opb_fifo_flg(3),
        opb_m_tx_en      => opb_m_tx_en,
        opb_m_tx_data    => opb_m_tx_data,
        opb_tx_dma_ctl   => opb_tx_dma_ctl,
        opb_tx_dma_addr  => opb_tx_dma_addr,
        opb_tx_dma_num   => opb_tx_dma_num,
        opb_tx_dma_done  => opb_fifo_flg(13),
        opb_m_rx_req     => opb_fifo_flg(6),
        opb_m_rx_en      => opb_m_rx_en,
        opb_m_rx_data    => opb_m_rx_data,
        opb_rx_dma_ctl   => opb_rx_dma_ctl,
        opb_rx_dma_addr  => opb_rx_dma_addr,
        opb_rx_dma_num   => opb_rx_dma_num,
        opb_rx_dma_done  => opb_fifo_flg(14),
        opb_abort_flg    => opb_abort_flg,
        opb_m_last_block => opb_m_last_block);
  end generate dma_enable;
 
  dma_disable : if (C_DMA_EN = false) generate
    M_request        <= '0';
    M_busLock        <= '0';
    M_ABus           <= (others => '0');
    M_BE             <= (others => '0');
    M_DBus           <= (others => '0');
    M_RNW            <= '0';
    M_select         <= '0';
    M_seqAddr        <= '0';
    opb_m_tx_en      <= '0';
    opb_m_tx_data    <= (others => '0');
    opb_fifo_flg(13) <= '0';
    opb_m_rx_en      <= '0';
    opb_fifo_flg(14) <= '0';
  end generate dma_disable;
 
  --* Shift-Register 
  shift_register_1 : shift_register
    generic map (
      C_SR_WIDTH  => C_SR_WIDTH,
      C_MSB_FIRST => C_MSB_FIRST,
      C_CPOL      => C_CPOL,
      C_PHA       => C_PHA)
    port map (
      rst         => rst,
      opb_ctl_reg => opb_ctl_reg,
      sclk        => sclk_bufr,
      ss_n        => ss_n,
      mosi        => mosi,
      miso_o      => miso_o,
      miso_i      => miso_i,
      miso_t      => miso_t,
      sr_tx_clk   => sr_tx_clk,
      sr_tx_en    => sr_tx_en,
      sr_tx_data  => sr_tx_data,
      sr_rx_clk   => sr_rx_clk,
      sr_rx_en    => sr_rx_en,
      sr_rx_data  => sr_rx_data);
 
  --* Transmit FIFO
  tx_fifo_1 : fifo
    generic map (
      C_FIFO_WIDTH      => C_SR_WIDTH,
      C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,
      C_SYNC_TO         => "WR")
    port map (
      -- global
      rst               => rst,
      prog_full_thresh  => tx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0),
      prog_empty_thresh => tx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH),
      -- write port
      wr_clk            => OPB_Clk,
      wr_en             => fifo_tx_en,
      din               => fifo_tx_data,
      -- flags
      prog_full         => opb_fifo_flg(0),
      full              => opb_fifo_flg(1),
      overflow          => opb_fifo_flg(2),
      -- read port
      rd_clk            => sr_tx_clk,
      rd_en             => sr_tx_en,
      dout              => sr_tx_data,
      -- flags
      prog_empty        => opb_fifo_flg(3),
      empty             => opb_fifo_flg(4),
      underflow         => opb_fifo_flg(5));
 
  fifo_tx_en   <= opb_s_tx_en or opb_m_tx_en;
  fifo_tx_data <= opb_tx_crc_value when (C_CRC_EN and tx_crc_insert = '1') else
                  opb_m_tx_data when (opb_tx_dma_ctl(0) = '1') else
                  opb_s_tx_data;
 
  --* Receive FIFO
  rx_fifo_1 : fifo
    generic map (
      C_FIFO_WIDTH      => C_SR_WIDTH,
      C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,
      C_SYNC_TO         => "RD")
    port map (
      -- global
      rst               => rst,
      prog_full_thresh  => rx_thresh(C_FIFO_SIZE_WIDTH-1 downto 0),
      prog_empty_thresh => rx_thresh((2*C_FIFO_SIZE_WIDTH)-1 downto C_FIFO_SIZE_WIDTH),
      -- write port
      wr_clk            => sr_rx_clk,
      wr_en             => sr_rx_en,
      din               => sr_rx_data,
      -- flags
      prog_full         => opb_fifo_flg(6),
      full              => opb_fifo_flg(7),
      overflow          => opb_fifo_flg(8),
      -- read port
      rd_clk            => opb_clk,
      rd_en             => fifo_rx_en,
      dout              => fifo_rx_data,
      -- flags
      prog_empty        => opb_fifo_flg(9),
      empty             => opb_fifo_flg(10),
      underflow         => opb_fifo_flg(11));
 
  fifo_rx_en    <= opb_s_rx_en or opb_m_rx_en;
  opb_s_rx_data <= fifo_rx_data;
  opb_m_rx_data <= fifo_rx_data;
 
  rst <= OPB_Rst or opb_ctl_reg(C_OPB_CTL_REG_RST);
 
  opb_fifo_flg(12) <= ss_n;
  opb_fifo_flg(15) <= opb_abort_flg;
 
 
 
  -- Bit 0 : TX_PROG_EMPTY
  opb_irq_flg(0)  <= opb_fifo_flg(3);
  -- Bit 1 : TX_EMPTY
  opb_irq_flg(1)  <= opb_fifo_flg(4);
  -- Bit 2 : TX_Underflow
  opb_irq_flg(2)  <= opb_fifo_flg(5);
  -- Bit 3 : RX_PROG_FULL
  opb_irq_flg(3)  <= opb_fifo_flg(6);
  -- Bit 4 : RX_FULL
  opb_irq_flg(4)  <= opb_fifo_flg(7);
  -- Bit 5 : RX_Overflow
  opb_irq_flg(5)  <= opb_fifo_flg(8);
  -- Bit 6:  CS_H_TO_L
  opb_irq_flg(6)  <= not opb_fifo_flg(12);
  -- Bit 7:  CS_L_TO_H
  opb_irq_flg(7)  <= opb_fifo_flg(12);
  -- Bit 8: TX DMA Done
  opb_irq_flg(8)  <= opb_fifo_flg(13);
  -- Bit 9: RX DMA Done
  opb_irq_flg(9)  <= opb_fifo_flg(14);
  -- Bit 10: DMA Transfer Abort
  opb_irq_flg(10) <= opb_abort_flg;
 
  --* IRQ Enable, Detection and Flags Control
  irq_gen : for i in 0 to C_NUM_INT-1 generate
    irq_ctl_1 : irq_ctl
      generic map (
        C_ACTIVE_EDGE => '1')
      port map (
        rst          => rst,
        clk          => OPB_Clk,
        opb_fifo_flg => opb_irq_flg(i),
        opb_ier      => opb_ier(i),
        opb_isr      => opb_isr(i),
        opb_isr_clr  => opb_isr_clr(i));
  end generate irq_gen;
 
  -- assert irq if one Interupt Status bit set
  opb_irq <= '1' when (conv_integer(opb_isr) /= 0 and opb_dgie = '1') else
             '0';
 
 
  -----------------------------------------------------------------------------
 
  -- clear start_value at power up and soft_reset
  crc_en  <= opb_ctl_reg(C_OPB_CTL_REG_CRC_EN);
  crc_clr <= opb_ctl_reg(C_OPB_CTL_REG_CRC_CLR) or rst;
 
  crc_gen : if (C_CRC_EN) generate
    crc_core_1 : crc_core
      generic map (
        C_SR_WIDTH => C_SR_WIDTH)
      port map (
        rst              => rst,
        opb_clk          => opb_clk,
        crc_en           => crc_en,
        crc_clr          => crc_clr,
        opb_m_last_block => opb_m_last_block,
        fifo_rx_en       => fifo_rx_en,
        fifo_rx_data     => fifo_rx_data,
        opb_rx_crc_value => opb_rx_crc_value,
        fifo_tx_en       => fifo_tx_en,
        fifo_tx_data     => fifo_tx_data,
        tx_crc_insert    => tx_crc_insert,
        opb_tx_crc_value => opb_tx_crc_value);
  end generate crc_gen;
 
 
end behavior;

Line No.	Rev	Author	Line
1	2	dkoethe	`-------------------------------------------------------------------------------`
2			`--*`
3			`--* @short Top entity of the project opi_spi_slave`
4			`--*`
5			`--* @generic C_FAMILY virtex-4 and generic supported`
6			`--* @author: Daniel K�the`
7	4	dkoethe	`--* @version: 1.1`
8			`--* @date: 2007-11-19`
9	2	dkoethe	`--/`
10	4	dkoethe	`-- Version 1.1`
11			`-- Bugfix`
12			`-- IRQ-Flag RX_Overflow shows prog_empty insteed rx_overflow`
13			`-- opb_irq_flg(5) <= opb_fifo_flg(9); to opb_irq_flg(5) <= opb_fifo_flg(8);`
14
15	2	dkoethe	`-------------------------------------------------------------------------------`
16
17			`library ieee;`
18			`use ieee.std_logic_1164.all;`
19			`use IEEE.STD_LOGIC_UNSIGNED.all;`
20
21
22			`library UNISIM;`
23			`use UNISIM.vcomponents.all;`
24
25			`library work;`
26			`use work.opb_spi_slave_pack.all;`
27
28
29			`entity opb_spi_slave is`
30
31			`generic (`
32			`C_BASEADDR : std_logic_vector(0 to 31) := X"00000000";`
33			`C_HIGHADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";`
34			`C_USER_ID_CODE : integer := 0;`
35			`C_OPB_AWIDTH : integer := 32;`
36			`C_OPB_DWIDTH : integer := 32;`
37
38			`C_FAMILY : string := "virtex4";`
39			`-- user ports`
40			`C_SR_WIDTH : integer := 8;`
41			`C_MSB_FIRST : boolean := true;`
42			`C_CPOL : integer range 0 to 1 := 0;`
43			`C_PHA : integer range 0 to 1 := 0;`
44			`C_FIFO_SIZE_WIDTH : integer range 4 to 7 := 5; -- depth 32`
45	23	dkoethe	`C_DMA_EN : boolean := false;`
46			`C_CRC_EN : boolean := false);`
47	2	dkoethe
48			`port (`
49			`-- OPB signals (Slave Side)`
50			`OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);`
51			`OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);`
52			`OPB_Clk : in std_logic;`
53			`OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);`
54			`OPB_RNW : in std_logic;`
55			`OPB_Rst : in std_logic;`
56			`OPB_select : in std_logic;`
57			`OPB_seqAddr : in std_logic;`
58			`Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);`
59			`Sln_errAck : out std_logic;`
60			`Sln_retry : out std_logic;`
61			`Sln_toutSup : out std_logic;`
62			`Sln_xferAck : out std_logic;`
63
64			`-- OPB signals (Master Side)`
65			`-- Arbitration`
66			`M_request : out std_logic;`
67			`MOPB_MGrant : in std_logic;`
68			`M_busLock : out std_logic;`
69			`--`
70			`M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);`
71			`M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);`
72			`M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);`
73			`M_RNW : out std_logic;`
74			`M_select : out std_logic;`
75			`M_seqAddr : out std_logic;`
76			`MOPB_errAck : in std_logic;`
77			`MOPB_retry : in std_logic;`
78			`MOPB_timeout : in std_logic;`
79			`MOPB_xferAck : in std_logic;`
80			`-- spi ports`
81			`sclk : in std_logic;`
82			`ss_n : in std_logic;`
83			`mosi : in std_logic;`
84			`miso_o : out std_logic;`
85			`miso_i : in std_logic;`
86			`miso_t : out std_logic;`
87			`-- irq output`
88			`opb_irq : out std_logic);`
89
90			`end opb_spi_slave;`
91
92			`architecture behavior of opb_spi_slave is`
93
94			`component opb_if`
95			`generic (`
96			`C_BASEADDR : std_logic_vector(0 to 31);`
97			`C_HIGHADDR : std_logic_vector(0 to 31);`
98			`C_USER_ID_CODE : integer;`
99			`C_OPB_AWIDTH : integer;`
100			`C_OPB_DWIDTH : integer;`
101			`C_FAMILY : string;`
102			`C_SR_WIDTH : integer;`
103			`C_FIFO_SIZE_WIDTH : integer;`
104	23	dkoethe	`C_DMA_EN : boolean;`
105			`C_CRC_EN : boolean);`
106	2	dkoethe	`port (`
107	23	dkoethe	`OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH-1);`
108			`OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8-1);`
109			`OPB_Clk : in std_logic;`
110			`OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);`
111			`OPB_RNW : in std_logic;`
112			`OPB_Rst : in std_logic;`
113			`OPB_select : in std_logic;`
114			`OPB_seqAddr : in std_logic;`
115			`Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);`
116			`Sln_errAck : out std_logic;`
117			`Sln_retry : out std_logic;`
118			`Sln_toutSup : out std_logic;`
119			`Sln_xferAck : out std_logic;`
120			`opb_s_tx_en : out std_logic;`
121			`opb_s_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0);`
122			`opb_s_rx_en : out std_logic;`
123			`opb_s_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
124			`opb_ctl_reg : out std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);`
125			`tx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);`
126			`rx_thresh : out std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);`
127			`opb_fifo_flg : in std_logic_vector(C_NUM_FLG-1 downto 0);`
128			`opb_dgie : out std_logic;`
129			`opb_ier : out std_logic_vector(C_NUM_INT-1 downto 0);`
130			`opb_isr : in std_logic_vector(C_NUM_INT-1 downto 0);`
131			`opb_isr_clr : out std_logic_vector(C_NUM_INT-1 downto 0);`
132			`opb_tx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);`
133			`opb_tx_dma_ctl : out std_logic_vector(0 downto 0);`
134			`opb_tx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);`
135			`opb_rx_dma_addr : out std_logic_vector(C_OPB_DWIDTH-1 downto 0);`
136			`opb_rx_dma_ctl : out std_logic_vector(0 downto 0);`
137			`opb_rx_dma_num : out std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);`
138			`opb_rx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
139			`opb_tx_crc_value : in std_logic_vector(C_SR_WIDTH-1 downto 0));`
140
141	2	dkoethe	`end component;`
142
143
144			`component opb_m_if`
145			`generic (`
146			`C_BASEADDR : std_logic_vector(0 to 31);`
147			`C_HIGHADDR : std_logic_vector(0 to 31);`
148			`C_USER_ID_CODE : integer;`
149			`C_OPB_AWIDTH : integer;`
150			`C_OPB_DWIDTH : integer;`
151			`C_FAMILY : string;`
152			`C_SR_WIDTH : integer;`
153			`C_MSB_FIRST : boolean;`
154			`C_CPOL : integer range 0 to 1;`
155			`C_PHA : integer range 0 to 1;`
156			`C_FIFO_SIZE_WIDTH : integer range 4 to 7);`
157			`port (`
158	23	dkoethe	`OPB_Clk : in std_logic;`
159			`OPB_Rst : in std_logic;`
160			`OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH-1);`
161			`M_request : out std_logic;`
162			`MOPB_MGrant : in std_logic;`
163			`M_busLock : out std_logic;`
164			`M_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);`
165			`M_BE : out std_logic_vector(0 to C_OPB_DWIDTH/8-1);`
166			`M_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);`
167			`M_RNW : out std_logic;`
168			`M_select : out std_logic;`
169			`M_seqAddr : out std_logic;`
170			`MOPB_errAck : in std_logic;`
171			`MOPB_retry : in std_logic;`
172			`MOPB_timeout : in std_logic;`
173			`MOPB_xferAck : in std_logic;`
174			`opb_m_tx_req : in std_logic;`
175			`opb_m_tx_en : out std_logic;`
176			`opb_m_tx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0);`
177			`opb_tx_dma_ctl : in std_logic_vector(0 downto 0);`
178			`opb_tx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);`
179			`opb_tx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);`
180			`opb_tx_dma_done : out std_logic;`
181			`opb_m_rx_req : in std_logic;`
182			`opb_m_rx_en : out std_logic;`
183			`opb_m_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
184			`opb_rx_dma_ctl : in std_logic_vector(0 downto 0);`
185			`opb_rx_dma_addr : in std_logic_vector(C_OPB_DWIDTH-1 downto 0);`
186			`opb_rx_dma_num : in std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);`
187			`opb_rx_dma_done : out std_logic;`
188			`opb_abort_flg : out std_logic;`
189			`opb_m_last_block : out std_logic);`
190	2	dkoethe	`end component;`
191
192			`component shift_register`
193			`generic (`
194			`C_SR_WIDTH : integer;`
195			`C_MSB_FIRST : boolean;`
196			`C_CPOL : integer range 0 to 1;`
197			`C_PHA : integer range 0 to 1);`
198			`port (`
199			`rst : in std_logic;`
200			`opb_ctl_reg : in std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);`
201			`sclk : in std_logic;`
202			`ss_n : in std_logic;`
203			`mosi : in std_logic;`
204			`miso_o : out std_logic;`
205			`miso_i : in std_logic;`
206			`miso_t : out std_logic;`
207			`sr_tx_clk : out std_logic;`
208			`sr_tx_en : out std_logic;`
209			`sr_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
210			`sr_rx_clk : out std_logic;`
211			`sr_rx_en : out std_logic;`
212			`sr_rx_data : out std_logic_vector(C_SR_WIDTH-1 downto 0));`
213			`end component;`
214
215			`component fifo`
216			`generic (`
217			`C_FIFO_WIDTH : integer;`
218			`C_FIFO_SIZE_WIDTH : integer;`
219			`C_SYNC_TO : string);`
220			`port (`
221			`rst : in std_logic;`
222			`wr_clk : in std_logic;`
223			`wr_en : in std_logic;`
224			`din : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
225			`rd_clk : in std_logic;`
226			`rd_en : in std_logic;`
227			`dout : out std_logic_vector(C_SR_WIDTH-1 downto 0);`
228			`empty : out std_logic;`
229			`full : out std_logic;`
230			`overflow : out std_logic;`
231			`underflow : out std_logic;`
232			`prog_empty_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0);`
233			`prog_full_thresh : in std_logic_vector(C_FIFO_SIZE_WIDTH-1 downto 0);`
234			`prog_empty : out std_logic;`
235			`prog_full : out std_logic);`
236			`end component;`
237
238			`component irq_ctl`
239			`generic (`
240			`C_ACTIVE_EDGE : std_logic);`
241			`port (`
242			`rst : in std_logic;`
243			`clk : in std_logic;`
244			`opb_fifo_flg : in std_logic;`
245			`opb_ier : in std_logic;`
246			`opb_isr : out std_logic;`
247			`opb_isr_clr : in std_logic);`
248			`end component;`
249
250	23	dkoethe	`component crc_core`
251			`generic (`
252			`C_SR_WIDTH : integer);`
253			`port (`
254			`rst : in std_logic;`
255			`opb_clk : in std_logic;`
256			`crc_en : in std_logic;`
257			`crc_clr : in std_logic;`
258			`opb_m_last_block : in std_logic;`
259			`fifo_rx_en : in std_logic;`
260			`fifo_rx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
261			`opb_rx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0);`
262			`fifo_tx_en : in std_logic;`
263			`fifo_tx_data : in std_logic_vector(C_SR_WIDTH-1 downto 0);`
264			`tx_crc_insert : out std_logic;`
265			`opb_tx_crc_value : out std_logic_vector(C_SR_WIDTH-1 downto 0));`
266			`end component;`
267
268	2	dkoethe	`-- opb_if`
269			`signal opb_ctl_reg : std_logic_vector(C_OPB_CTL_REG_WIDTH-1 downto 0);`
270
271			`signal opb_s_tx_en : std_logic;`
272			`signal opb_s_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
273			`signal opb_s_rx_en : std_logic;`
274			`signal opb_s_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
275
276			`signal tx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);`
277			`signal rx_thresh : std_logic_vector((2*C_FIFO_SIZE_WIDTH)-1 downto 0);`
278
279			`signal opb_tx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0);`
280			`signal opb_tx_dma_ctl : std_logic_vector(0 downto 0);`
281	10	dkoethe	`signal opb_tx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);`
282	2	dkoethe	`signal opb_rx_dma_addr : std_logic_vector(C_OPB_DWIDTH-1 downto 0);`
283			`signal opb_rx_dma_ctl : std_logic_vector(0 downto 0);`
284	10	dkoethe	`signal opb_rx_dma_num : std_logic_vector(C_WIDTH_DMA_NUM-1 downto 0);`
285	2	dkoethe
286	23	dkoethe	`signal opb_rx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);`
287			`signal opb_tx_crc_value : std_logic_vector(C_SR_WIDTH-1 downto 0);`
288
289	2	dkoethe	`-- opb_m_if`
290	23	dkoethe	`signal opb_m_tx_en : std_logic;`
291			`signal opb_m_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
292			`signal opb_m_rx_en : std_logic;`
293			`signal opb_m_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
294			`signal opb_abort_flg : std_logic;`
295			`signal opb_m_last_block : std_logic;`
296	2	dkoethe
297			`-- shift_register`
298			`signal sr_tx_clk : std_logic;`
299			`signal sr_tx_en : std_logic;`
300			`signal sr_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
301			`signal sr_rx_clk : std_logic;`
302			`signal sr_rx_en : std_logic;`
303			`signal sr_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
304
305			`signal sclk_ibuf : std_logic;`
306			`signal sclk_bufr : std_logic;`
307
308			`signal opb_fifo_flg : std_logic_vector(C_NUM_FLG-1 downto 0);`
309			`signal opb_irq_flg : std_logic_vector(C_NUM_INT-1 downto 0) := (others => '0');`
310			`signal rst : std_logic;`
311
312
313			`signal opb_dgie : std_logic;`
314			`signal opb_ier : std_logic_vector(C_NUM_INT-1 downto 0);`
315			`signal opb_isr : std_logic_vector(C_NUM_INT-1 downto 0);`
316			`signal opb_isr_clr : std_logic_vector(C_NUM_INT-1 downto 0);`
317
318			`-- opb_spi_slave`
319			`signal fifo_tx_en : std_logic;`
320			`signal fifo_tx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
321			`signal fifo_rx_en : std_logic;`
322			`signal fifo_rx_data : std_logic_vector(C_SR_WIDTH-1 downto 0);`
323	23	dkoethe
324			`-- rx crc_core`
325			`signal crc_clr : std_logic;`
326			`signal crc_en : std_logic;`
327			`signal tx_crc_insert : std_logic;`
328
329	2	dkoethe	`begin -- behavior`
330
331			`--*`
332			`virtex4_slk_buf : if C_FAMILY = "virtex4" generate`
333			`--* If C_FAMILY=Virtex-4 use "IBUF"`
334			`IBUF_1 : IBUF`
335			`port map (`
336			`I => sclk,`
337			`O => sclk_ibuf);`
338
339			`--* If C_FAMILY=Virtex-4 use "BUFR"`
340			`BUFR_1 : BUFR`
341			`generic map (`
342			`BUFR_DIVIDE => "BYPASS",`
343			`SIM_DEVICE => "VIRTEX4")`
344			`port map (`
345			`O => sclk_bufr,`
346			`CE => '0',`
347			`CLR => '0',`
348			`I => sclk_ibuf);`
349			`end generate virtex4_slk_buf;`
350
351			`generic_sclk_buf : if C_FAMILY /= "virtex4" generate`
352			`sclk_bufr <= sclk;`
353			`end generate generic_sclk_buf;`
354
355			`--* OPB-Slave Interface(Register-Interface)`
356			`opb_if_2 : opb_if`
357			`generic map (`
358			`C_BASEADDR => C_BASEADDR,`
359			`C_HIGHADDR => C_HIGHADDR,`
360			`C_USER_ID_CODE => C_USER_ID_CODE,`
361			`C_OPB_AWIDTH => C_OPB_AWIDTH,`
362			`C_OPB_DWIDTH => C_OPB_DWIDTH,`
363			`C_FAMILY => C_FAMILY,`
364			`C_SR_WIDTH => C_SR_WIDTH,`
365			`C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,`
366	23	dkoethe	`C_DMA_EN => C_DMA_EN,`
367			`C_CRC_EN => C_CRC_EN)`
368	2	dkoethe	`port map (`
369	23	dkoethe	`OPB_ABus => OPB_ABus,`
370			`OPB_BE => OPB_BE,`
371			`OPB_Clk => OPB_Clk,`
372			`OPB_DBus => OPB_DBus,`
373			`OPB_RNW => OPB_RNW,`
374			`OPB_Rst => OPB_Rst,`
375			`OPB_select => OPB_select,`
376			`OPB_seqAddr => OPB_seqAddr,`
377			`Sln_DBus => Sln_DBus,`
378			`Sln_errAck => Sln_errAck,`
379			`Sln_retry => Sln_retry,`
380			`Sln_toutSup => Sln_toutSup,`
381			`Sln_xferAck => Sln_xferAck,`
382			`opb_s_tx_en => opb_s_tx_en,`
383			`opb_s_tx_data => opb_s_tx_data,`
384			`opb_s_rx_en => opb_s_rx_en,`
385			`opb_s_rx_data => opb_s_rx_data,`
386			`opb_ctl_reg => opb_ctl_reg,`
387			`tx_thresh => tx_thresh,`
388			`rx_thresh => rx_thresh,`
389			`opb_fifo_flg => opb_fifo_flg,`
390			`opb_dgie => opb_dgie,`
391			`opb_ier => opb_ier,`
392			`opb_isr => opb_isr,`
393			`opb_isr_clr => opb_isr_clr,`
394			`opb_tx_dma_addr => opb_tx_dma_addr,`
395			`opb_tx_dma_ctl => opb_tx_dma_ctl,`
396			`opb_tx_dma_num => opb_tx_dma_num,`
397			`opb_rx_dma_addr => opb_rx_dma_addr,`
398			`opb_rx_dma_ctl => opb_rx_dma_ctl,`
399			`opb_rx_dma_num => opb_rx_dma_num,`
400			`opb_rx_crc_value => opb_rx_crc_value,`
401			`opb_tx_crc_value => opb_tx_crc_value);`
402	2	dkoethe
403			`--* OPB-Master-Interface`
404			`--*`
405			`--* (DMA Read/Write Transfers to TX/RX-FIFO)`
406
407			`dma_enable : if (C_DMA_EN = true) generate`
408			`opb_m_if_1 : opb_m_if`
409			`generic map (`
410			`C_BASEADDR => C_BASEADDR,`
411			`C_HIGHADDR => C_HIGHADDR,`
412			`C_USER_ID_CODE => C_USER_ID_CODE,`
413			`C_OPB_AWIDTH => C_OPB_AWIDTH,`
414			`C_OPB_DWIDTH => C_OPB_DWIDTH,`
415			`C_FAMILY => C_FAMILY,`
416			`C_SR_WIDTH => C_SR_WIDTH,`
417			`C_MSB_FIRST => C_MSB_FIRST,`
418			`C_CPOL => C_CPOL,`
419			`C_PHA => C_PHA,`
420			`C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH)`
421			`port map (`
422	23	dkoethe	`OPB_Clk => OPB_Clk,`
423			`OPB_Rst => OPB_Rst,`
424			`OPB_DBus => OPB_DBus,`
425			`M_request => M_request,`
426			`MOPB_MGrant => MOPB_MGrant,`
427			`M_busLock => M_busLock,`
428			`M_ABus => M_ABus,`
429			`M_BE => M_BE,`
430			`M_DBus => M_DBus,`
431			`M_RNW => M_RNW,`
432			`M_select => M_select,`
433			`M_seqAddr => M_seqAddr,`
434			`MOPB_errAck => MOPB_errAck,`
435			`MOPB_retry => MOPB_retry,`
436			`MOPB_timeout => MOPB_timeout,`
437			`MOPB_xferAck => MOPB_xferAck,`
438			`opb_m_tx_req => opb_fifo_flg(3),`
439			`opb_m_tx_en => opb_m_tx_en,`
440			`opb_m_tx_data => opb_m_tx_data,`
441			`opb_tx_dma_ctl => opb_tx_dma_ctl,`
442			`opb_tx_dma_addr => opb_tx_dma_addr,`
443			`opb_tx_dma_num => opb_tx_dma_num,`
444			`opb_tx_dma_done => opb_fifo_flg(13),`
445			`opb_m_rx_req => opb_fifo_flg(6),`
446			`opb_m_rx_en => opb_m_rx_en,`
447			`opb_m_rx_data => opb_m_rx_data,`
448			`opb_rx_dma_ctl => opb_rx_dma_ctl,`
449			`opb_rx_dma_addr => opb_rx_dma_addr,`
450			`opb_rx_dma_num => opb_rx_dma_num,`
451			`opb_rx_dma_done => opb_fifo_flg(14),`
452			`opb_abort_flg => opb_abort_flg,`
453			`opb_m_last_block => opb_m_last_block);`
454	2	dkoethe	`end generate dma_enable;`
455
456			`dma_disable : if (C_DMA_EN = false) generate`
457			`M_request <= '0';`
458			`M_busLock <= '0';`
459			`M_ABus <= (others => '0');`
460			`M_BE <= (others => '0');`
461			`M_DBus <= (others => '0');`
462			`M_RNW <= '0';`
463			`M_select <= '0';`
464			`M_seqAddr <= '0';`
465			`opb_m_tx_en <= '0';`
466			`opb_m_tx_data <= (others => '0');`
467			`opb_fifo_flg(13) <= '0';`
468			`opb_m_rx_en <= '0';`
469			`opb_fifo_flg(14) <= '0';`
470			`end generate dma_disable;`
471
472			`--* Shift-Register`
473			`shift_register_1 : shift_register`
474			`generic map (`
475			`C_SR_WIDTH => C_SR_WIDTH,`
476			`C_MSB_FIRST => C_MSB_FIRST,`
477			`C_CPOL => C_CPOL,`
478			`C_PHA => C_PHA)`
479			`port map (`
480			`rst => rst,`
481			`opb_ctl_reg => opb_ctl_reg,`
482			`sclk => sclk_bufr,`
483			`ss_n => ss_n,`
484			`mosi => mosi,`
485			`miso_o => miso_o,`
486			`miso_i => miso_i,`
487			`miso_t => miso_t,`
488			`sr_tx_clk => sr_tx_clk,`
489			`sr_tx_en => sr_tx_en,`
490			`sr_tx_data => sr_tx_data,`
491			`sr_rx_clk => sr_rx_clk,`
492			`sr_rx_en => sr_rx_en,`
493			`sr_rx_data => sr_rx_data);`
494
495			`--* Transmit FIFO`
496			`tx_fifo_1 : fifo`
497			`generic map (`
498			`C_FIFO_WIDTH => C_SR_WIDTH,`
499			`C_FIFO_SIZE_WIDTH => C_FIFO_SIZE_WIDTH,`
500			`C_SYNC_TO => "WR")`

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[/] [spi_slave/] [trunk/] [pcore/] [opb_spi_slave_v1_00_a/] [hdl/] [vhdl/] [opb_spi_slave.vhd] - Blame information for rev 23