URL https://opencores.org/ocsvn/spiadc/spiadc/trunk

Subversion Repositories spiadc

[/] [spiadc/] [trunk/] [TestBench/] [recv-master-tb.vht] - Blame information for rev 2

Details | Compare with Previous | View Log


-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors.  Please refer to the
-- applicable agreement for further details.
 
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "06/12/2009 19:55:56"
 
-- Vhdl Self-Checking Test Bench (with test vectors) for design :       RecvMasterTb
--
-- Simulation tool : 3rd Party
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY RecvMasterTb_vhd_vec_tst IS
END RecvMasterTb_vhd_vec_tst;
ARCHITECTURE RecvMasterTb_arch OF RecvMasterTb_vhd_vec_tst IS
-- constants
-- signals
SIGNAL CLC : STD_LOGIC;
SIGNAL CotinueStart : STD_LOGIC;
SIGNAL nSS : STD_LOGIC;
SIGNAL ready : STD_LOGIC;
SIGNAL Res : STD_LOGIC;
SIGNAL SCK : STD_LOGIC;
SIGNAL SDI : STD_LOGIC;
SIGNAL SDO : STD_LOGIC_VECTOR(9 DOWNTO 0);
SIGNAL ShutDown : STD_LOGIC;
SIGNAL Start : STD_LOGIC;
COMPONENT RecvMasterTb
        PORT (
        CLC : IN STD_LOGIC;
        CotinueStart : IN STD_LOGIC;
        nSS : OUT STD_LOGIC;
        ready : OUT STD_LOGIC;
        Res : IN STD_LOGIC;
        SCK : OUT STD_LOGIC;
        SDI : IN STD_LOGIC;
        SDO : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
        ShutDown : IN STD_LOGIC;
        Start : IN STD_LOGIC
        );
END COMPONENT;
BEGIN
        i1 : RecvMasterTb
        PORT MAP (
-- list connections between master ports and signals
        CLC => CLC,
        CotinueStart => CotinueStart,
        nSS => nSS,
        ready => ready,
        Res => Res,
        SCK => SCK,
        SDI => SDI,
        SDO => SDO,
        ShutDown => ShutDown,
        Start => Start
        );
 
-- CLC
t_prcs_CLC: PROCESS
BEGIN
LOOP
        CLC <= '0';
        WAIT FOR 25000 ps;
        CLC <= '1';
        WAIT FOR 25000 ps;
        IF (NOW >= 100000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_CLC;
 
-- CotinueStart
t_prcs_CotinueStart: PROCESS
BEGIN
        CotinueStart <= '0';
        WAIT FOR 25600000 ps;
        CotinueStart <= '1';
        WAIT FOR 3200000 ps;
        CotinueStart <= '0';
        WAIT FOR 3200000 ps;
        CotinueStart <= '1';
        WAIT FOR 3840000 ps;
        CotinueStart <= '0';
WAIT;
END PROCESS t_prcs_CotinueStart;
 
-- Res
t_prcs_Res: PROCESS
BEGIN
        Res <= '0';
        WAIT FOR 20000 ps;
        Res <= '1';
        WAIT FOR 40000 ps;
        Res <= '0';
WAIT;
END PROCESS t_prcs_Res;
 
-- ShutDown
t_prcs_ShutDown: PROCESS
BEGIN
        ShutDown <= '0';
        WAIT FOR 8800000 ps;
        ShutDown <= '1';
        WAIT FOR 3200000 ps;
        ShutDown <= '0';
        WAIT FOR 3040000 ps;
        ShutDown <= '1';
        WAIT FOR 4160000 ps;
        ShutDown <= '0';
        WAIT FOR 1600000 ps;
        ShutDown <= '1';
        WAIT FOR 960000 ps;
        ShutDown <= '0';
WAIT;
END PROCESS t_prcs_ShutDown;
 
-- Start
t_prcs_Start: PROCESS
BEGIN
        Start <= '0';
        WAIT FOR 420000 ps;
        Start <= '1';
        WAIT FOR 20000 ps;
        Start <= '0';
        WAIT FOR 2440000 ps;
        Start <= '1';
        WAIT FOR 5040000 ps;
        Start <= '0';
        WAIT FOR 1120000 ps;
        Start <= '1';
        WAIT FOR 4640000 ps;
        Start <= '0';
        WAIT FOR 3440000 ps;
        Start <= '1';
        WAIT FOR 160000 ps;
        Start <= '0';
        WAIT FOR 8000000 ps;
        Start <= '1';
        WAIT FOR 160000 ps;
        Start <= '0';
        WAIT FOR 4800000 ps;
        Start <= '1';
        WAIT FOR 160000 ps;
        Start <= '0';
        WAIT FOR 1600000 ps;
        Start <= '1';
        WAIT FOR 160000 ps;
        Start <= '0';
WAIT;
END PROCESS t_prcs_Start;
 
-- SDI
t_prcs_SDI: PROCESS
BEGIN
        SDI <= '0';
        WAIT FOR 3120000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 480000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 160000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 320000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 960000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 160000 ps;
        SDI <= '1';
        WAIT FOR 160000 ps;
        SDI <= '0';
        WAIT FOR 160000 ps;
        SDI <= '1';
        WAIT FOR 480000 ps;
        SDI <= '0';
        WAIT FOR 800000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 560000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 320000 ps;
        SDI <= '1';
        WAIT FOR 320000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 160000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 400000 ps;
        SDI <= '0';
        WAIT FOR 11760000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 480000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 160000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 320000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 960000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 160000 ps;
        SDI <= '1';
        WAIT FOR 160000 ps;
        SDI <= '0';
        WAIT FOR 160000 ps;
        SDI <= '1';
        WAIT FOR 480000 ps;
        SDI <= '0';
        WAIT FOR 800000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 560000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 320000 ps;
        SDI <= '1';
        WAIT FOR 320000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 240000 ps;
        SDI <= '1';
        WAIT FOR 240000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 160000 ps;
        SDI <= '1';
        WAIT FOR 80000 ps;
        SDI <= '0';
        WAIT FOR 400000 ps;
        SDI <= '1';
        WAIT FOR 400000 ps;
        SDI <= '0';
WAIT;
END PROCESS t_prcs_SDI;
END RecvMasterTb_arch;

Browse

Tools

Subversion Repositories spiadc

[/] [spiadc/] [trunk/] [TestBench/] [recv-master-tb.vht] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	AlexRayne	`-- Copyright (C) 1991-2008 Altera Corporation`
2			`-- Your use of Altera Corporation's design tools, logic functions`
3			`-- and other software and tools, and its AMPP partner logic`
4			`-- functions, and any output files from any of the foregoing`
5			`-- (including device programming or simulation files), and any`
6			`-- associated documentation or information are expressly subject`
7			`-- to the terms and conditions of the Altera Program License`
8			`-- Subscription Agreement, Altera MegaCore Function License`
9			`-- Agreement, or other applicable license agreement, including,`
10			`-- without limitation, that your use is for the sole purpose of`
11			`-- programming logic devices manufactured by Altera and sold by`
12			`-- Altera or its authorized distributors. Please refer to the`
13			`-- applicable agreement for further details.`
14
15			`-- *****************************************************************************`
16			`-- This file contains a Vhdl test bench with test vectors .The test vectors`
17			`-- are exported from a vector file in the Quartus Waveform Editor and apply to`
18			`-- the top level entity of the current Quartus project .The user can use this`
19			`-- testbench to simulate his design using a third-party simulation tool .`
20			`-- *****************************************************************************`
21			`-- Generated on "06/12/2009 19:55:56"`
22
23			`-- Vhdl Self-Checking Test Bench (with test vectors) for design : RecvMasterTb`
24			`--`
25			`-- Simulation tool : 3rd Party`
26			`--`
27
28			`LIBRARY ieee;`
29			`USE ieee.std_logic_1164.all;`
30
31			`ENTITY RecvMasterTb_vhd_vec_tst IS`
32			`END RecvMasterTb_vhd_vec_tst;`
33			`ARCHITECTURE RecvMasterTb_arch OF RecvMasterTb_vhd_vec_tst IS`
34			`-- constants`
35			`-- signals`
36			`SIGNAL CLC : STD_LOGIC;`
37			`SIGNAL CotinueStart : STD_LOGIC;`
38			`SIGNAL nSS : STD_LOGIC;`
39			`SIGNAL ready : STD_LOGIC;`
40			`SIGNAL Res : STD_LOGIC;`
41			`SIGNAL SCK : STD_LOGIC;`
42			`SIGNAL SDI : STD_LOGIC;`
43			`SIGNAL SDO : STD_LOGIC_VECTOR(9 DOWNTO 0);`
44			`SIGNAL ShutDown : STD_LOGIC;`
45			`SIGNAL Start : STD_LOGIC;`
46			`COMPONENT RecvMasterTb`
47			`PORT (`
48			`CLC : IN STD_LOGIC;`
49			`CotinueStart : IN STD_LOGIC;`
50			`nSS : OUT STD_LOGIC;`
51			`ready : OUT STD_LOGIC;`
52			`Res : IN STD_LOGIC;`
53			`SCK : OUT STD_LOGIC;`
54			`SDI : IN STD_LOGIC;`
55			`SDO : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);`
56			`ShutDown : IN STD_LOGIC;`
57			`Start : IN STD_LOGIC`
58			`);`
59			`END COMPONENT;`
60			`BEGIN`
61			`i1 : RecvMasterTb`
62			`PORT MAP (`
63			`-- list connections between master ports and signals`
64			`CLC => CLC,`
65			`CotinueStart => CotinueStart,`
66			`nSS => nSS,`
67			`ready => ready,`
68			`Res => Res,`
69			`SCK => SCK,`
70			`SDI => SDI,`
71			`SDO => SDO,`
72			`ShutDown => ShutDown,`
73			`Start => Start`
74			`);`
75
76			`-- CLC`
77			`t_prcs_CLC: PROCESS`
78			`BEGIN`
79			`LOOP`
80			`CLC <= '0';`
81			`WAIT FOR 25000 ps;`
82			`CLC <= '1';`
83			`WAIT FOR 25000 ps;`
84			`IF (NOW >= 100000000 ps) THEN WAIT; END IF;`
85			`END LOOP;`
86			`END PROCESS t_prcs_CLC;`
87
88			`-- CotinueStart`
89			`t_prcs_CotinueStart: PROCESS`
90			`BEGIN`
91			`CotinueStart <= '0';`
92			`WAIT FOR 25600000 ps;`
93			`CotinueStart <= '1';`
94			`WAIT FOR 3200000 ps;`
95			`CotinueStart <= '0';`
96			`WAIT FOR 3200000 ps;`
97			`CotinueStart <= '1';`
98			`WAIT FOR 3840000 ps;`
99			`CotinueStart <= '0';`
100			`WAIT;`
101			`END PROCESS t_prcs_CotinueStart;`
102
103			`-- Res`
104			`t_prcs_Res: PROCESS`
105			`BEGIN`
106			`Res <= '0';`
107			`WAIT FOR 20000 ps;`
108			`Res <= '1';`
109			`WAIT FOR 40000 ps;`
110			`Res <= '0';`
111			`WAIT;`
112			`END PROCESS t_prcs_Res;`
113
114			`-- ShutDown`
115			`t_prcs_ShutDown: PROCESS`
116			`BEGIN`
117			`ShutDown <= '0';`
118			`WAIT FOR 8800000 ps;`
119			`ShutDown <= '1';`
120			`WAIT FOR 3200000 ps;`
121			`ShutDown <= '0';`
122			`WAIT FOR 3040000 ps;`
123			`ShutDown <= '1';`
124			`WAIT FOR 4160000 ps;`
125			`ShutDown <= '0';`
126			`WAIT FOR 1600000 ps;`
127			`ShutDown <= '1';`
128			`WAIT FOR 960000 ps;`
129			`ShutDown <= '0';`
130			`WAIT;`
131			`END PROCESS t_prcs_ShutDown;`
132
133			`-- Start`
134			`t_prcs_Start: PROCESS`
135			`BEGIN`
136			`Start <= '0';`
137			`WAIT FOR 420000 ps;`
138			`Start <= '1';`
139			`WAIT FOR 20000 ps;`
140			`Start <= '0';`
141			`WAIT FOR 2440000 ps;`
142			`Start <= '1';`
143			`WAIT FOR 5040000 ps;`
144			`Start <= '0';`
145			`WAIT FOR 1120000 ps;`
146			`Start <= '1';`
147			`WAIT FOR 4640000 ps;`
148			`Start <= '0';`
149			`WAIT FOR 3440000 ps;`
150			`Start <= '1';`
151			`WAIT FOR 160000 ps;`
152			`Start <= '0';`
153			`WAIT FOR 8000000 ps;`
154			`Start <= '1';`
155			`WAIT FOR 160000 ps;`
156			`Start <= '0';`
157			`WAIT FOR 4800000 ps;`
158			`Start <= '1';`
159			`WAIT FOR 160000 ps;`
160			`Start <= '0';`
161			`WAIT FOR 1600000 ps;`
162			`Start <= '1';`
163			`WAIT FOR 160000 ps;`
164			`Start <= '0';`
165			`WAIT;`
166			`END PROCESS t_prcs_Start;`
167
168			`-- SDI`
169			`t_prcs_SDI: PROCESS`
170			`BEGIN`
171			`SDI <= '0';`
172			`WAIT FOR 3120000 ps;`
173			`SDI <= '1';`
174			`WAIT FOR 80000 ps;`
175			`SDI <= '0';`
176			`WAIT FOR 480000 ps;`
177			`SDI <= '1';`
178			`WAIT FOR 240000 ps;`
179			`SDI <= '0';`
180			`WAIT FOR 400000 ps;`
181			`SDI <= '1';`
182			`WAIT FOR 160000 ps;`
183			`SDI <= '0';`
184			`WAIT FOR 240000 ps;`
185			`SDI <= '1';`
186			`WAIT FOR 320000 ps;`
187			`SDI <= '0';`
188			`WAIT FOR 240000 ps;`
189			`SDI <= '1';`
190			`WAIT FOR 960000 ps;`
191			`SDI <= '0';`
192			`WAIT FOR 400000 ps;`
193			`SDI <= '1';`
194			`WAIT FOR 80000 ps;`
195			`SDI <= '0';`
196			`WAIT FOR 240000 ps;`
197			`SDI <= '1';`
198			`WAIT FOR 240000 ps;`
199			`SDI <= '0';`
200			`WAIT FOR 160000 ps;`
201			`SDI <= '1';`
202			`WAIT FOR 160000 ps;`
203			`SDI <= '0';`
204			`WAIT FOR 160000 ps;`
205			`SDI <= '1';`
206			`WAIT FOR 480000 ps;`
207			`SDI <= '0';`
208			`WAIT FOR 800000 ps;`
209			`SDI <= '1';`
210			`WAIT FOR 240000 ps;`
211			`SDI <= '0';`
212			`WAIT FOR 560000 ps;`
213			`SDI <= '1';`
214			`WAIT FOR 240000 ps;`
215			`SDI <= '0';`
216			`WAIT FOR 320000 ps;`
217			`SDI <= '1';`
218			`WAIT FOR 320000 ps;`
219			`SDI <= '0';`
220			`WAIT FOR 240000 ps;`
221			`SDI <= '1';`
222			`WAIT FOR 240000 ps;`
223			`SDI <= '0';`
224			`WAIT FOR 400000 ps;`
225			`SDI <= '1';`
226			`WAIT FOR 240000 ps;`
227			`SDI <= '0';`
228			`WAIT FOR 240000 ps;`
229			`SDI <= '1';`
230			`WAIT FOR 240000 ps;`
231			`SDI <= '0';`
232			`WAIT FOR 400000 ps;`
233			`SDI <= '1';`
234			`WAIT FOR 80000 ps;`
235			`SDI <= '0';`
236			`WAIT FOR 160000 ps;`
237			`SDI <= '1';`
238			`WAIT FOR 80000 ps;`
239			`SDI <= '0';`
240			`WAIT FOR 400000 ps;`
241			`SDI <= '1';`
242			`WAIT FOR 400000 ps;`
243			`SDI <= '0';`
244			`WAIT FOR 11760000 ps;`
245			`SDI <= '1';`
246			`WAIT FOR 80000 ps;`
247			`SDI <= '0';`
248			`WAIT FOR 480000 ps;`
249			`SDI <= '1';`
250			`WAIT FOR 240000 ps;`
251			`SDI <= '0';`
252			`WAIT FOR 400000 ps;`
253			`SDI <= '1';`
254			`WAIT FOR 160000 ps;`
255			`SDI <= '0';`
256			`WAIT FOR 240000 ps;`
257			`SDI <= '1';`
258			`WAIT FOR 320000 ps;`
259			`SDI <= '0';`
260			`WAIT FOR 240000 ps;`
261			`SDI <= '1';`
262			`WAIT FOR 960000 ps;`
263			`SDI <= '0';`
264			`WAIT FOR 400000 ps;`
265			`SDI <= '1';`
266			`WAIT FOR 80000 ps;`
267			`SDI <= '0';`
268			`WAIT FOR 240000 ps;`
269			`SDI <= '1';`
270			`WAIT FOR 240000 ps;`
271			`SDI <= '0';`
272			`WAIT FOR 160000 ps;`
273			`SDI <= '1';`
274			`WAIT FOR 160000 ps;`
275			`SDI <= '0';`
276			`WAIT FOR 160000 ps;`
277			`SDI <= '1';`
278			`WAIT FOR 480000 ps;`
279			`SDI <= '0';`
280			`WAIT FOR 800000 ps;`
281			`SDI <= '1';`
282			`WAIT FOR 240000 ps;`
283			`SDI <= '0';`
284			`WAIT FOR 560000 ps;`
285			`SDI <= '1';`
286			`WAIT FOR 240000 ps;`
287			`SDI <= '0';`
288			`WAIT FOR 320000 ps;`
289			`SDI <= '1';`
290			`WAIT FOR 320000 ps;`
291			`SDI <= '0';`
292			`WAIT FOR 240000 ps;`
293			`SDI <= '1';`
294			`WAIT FOR 240000 ps;`
295			`SDI <= '0';`
296			`WAIT FOR 400000 ps;`
297			`SDI <= '1';`
298			`WAIT FOR 240000 ps;`
299			`SDI <= '0';`
300			`WAIT FOR 240000 ps;`
301			`SDI <= '1';`
302			`WAIT FOR 240000 ps;`
303			`SDI <= '0';`
304			`WAIT FOR 400000 ps;`
305			`SDI <= '1';`
306			`WAIT FOR 80000 ps;`
307			`SDI <= '0';`
308			`WAIT FOR 160000 ps;`
309			`SDI <= '1';`
310			`WAIT FOR 80000 ps;`
311			`SDI <= '0';`
312			`WAIT FOR 400000 ps;`
313			`SDI <= '1';`
314			`WAIT FOR 400000 ps;`
315			`SDI <= '0';`
316			`WAIT;`
317			`END PROCESS t_prcs_SDI;`
318			`END RecvMasterTb_arch;`