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johannesha |
Description of the internal SPI Flash controller:
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=================================================
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The SPI Flash controller occupies the following addresses in the
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DIY calculator address space:
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$F038 : Tx data register (write)
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$F018 : Rx data register (read)
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$F039 : command register (write)
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$F019 : status register (read)
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johannesha |
$F03A : address low register (write)
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$F03B : address mid register (write)
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$F03B : address high register (write)
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johannesha |
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The high address byte is fixed to $0F, denoting the last segment within
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the flash (8MBit type assumed).
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These are the bits of the status register:
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johannesha |
busy: $01
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tx empty: $02
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rx ready: $04
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wait for data: $08
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johannesha |
Other bits read as '0'.
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How to communicate with the SPI flash:
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--------------------------------------
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The SPI flash (ST M25P80 chip) understands the following commands:
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WREN ($06) .. write enable
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WRDI ($04) .. write disable
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RDSR ($05) .. read status register
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WRSR ($01) .. write status register
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RD ($03) .. read data
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F_RD ($0B) .. fast read data
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PP ($02) .. page program
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SE ($D8) .. sector erase
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BE ($C7) .. bulk erase
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DP ($B9) .. deep power down
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RES ($AB) .. read signature
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Additionally there is a pseudo-command defined for use with the SPI flash
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controller:
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NOP ($FF) .. no cmd to execute/end current command
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Command classification:
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-----------------------
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Write Enable (WREN) transmit 1 byte ... cmd (0x06)
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Write Disable (WRDI) (0x04)
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Bulk Erase (BE) (0xC7)
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Deep Power Down (DP) (0xB9)
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Write Status reg (WRSR) transmit 1 byte ... cmd (0x01)
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1 byte ... SR contents
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Sector Erase (SE) transmit 1 byte ... cmd (0xD8)
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3 bytes .. address
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Page Program (PP) transmit 1 byte ... cmd (0x02)
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3 bytes .. address
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1-256 bytes .. data
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Read Status reg (RDSR) transmit 1 byte ... cmd (0x05)
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receive 1 byte ... SR contents
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Read Signature (RES) transmit 1 byte ... cmd (0xAB)
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3 bytes .. dummy
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receive 1 byte ... the signature (0x13)
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Read Data (RD) transmit 1 byte ... cmd (0x03)
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3 bytes .. address
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receive n bytes .. data
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Fast Read Data (F_RD) transmit 1 byte ... cmd (0x0B)
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3 bytes .. address
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1 byte ... dummy
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receive n bytes .. data
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A command sequence depends on the command to be executed. For the simple
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commands (with no parameters) just the command is written to the SPI Flash
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controller command register (address $F039). The SPI controller shifts the
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cmd byte into the SPI flash. The more complex commands (with parameters)
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require that the parameters (e.g. address) are written first. The action
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of writing the command register triggers the transmission of the command
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plus all necessary parameter bytes to the SPI flash chip. With commands
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that receive a response (read commands) you have to wait for the response
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to arrive and then read the SPI flash controller data register ($F018).
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Examples
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--------
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1) issue the "Write Enable" command:
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LDA SPI_WREN
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STA [SPI_CMD]
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2) issue the "Read Signature" command:
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LDA SPI_RES
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STA [SPI_CMD]
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; wait for the response to arrive
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WAIT: LDA [SPI_STAT]
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AND SPI_RXR
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JZ [WAIT]
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; read the response
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LDA [SPI_RX]
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3) issue the "Sector Erase" command:
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johannesha |
; symbolic constant
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SECTOR .EQU $0F ; sector number
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.
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.
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.
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LDA SECTOR
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STA [SPI_AHI]
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johannesha |
LDA 0
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johannesha |
STA [SPI_AMID]
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johannesha |
STA [SPI_ALO]
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LDA SPI_SE
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STA [SPI_CMD]
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4) issue the "Read Data" command:
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; symbolic constant
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BUFSIZE: .EQU 100
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.
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.
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.
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; buffer reservation, in RAM
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BUF: .BLOCK BUFSIZE
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MAXBYTES: .WORD
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NUMBYTES: .WORD
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.
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.
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.
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; code:
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BLDX BUFSIZE
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BSTX [MAXBYTES]
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johannesha |
LDA SECTOR
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STA [SPI_AHI]
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johannesha |
LDA BUF
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johannesha |
STA [SPI_AMID]
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johannesha |
LDA BUF+1
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STA [SPI_ALO]
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LDA SPI_RD
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STA [SPI_CMD]
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BLDX 0
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BSTX [NUMBYTES]
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; now wait for the data to arrive
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LOOP: LDA [SPI_STAT]
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AND SPI_RXR
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JZ [LOOP]
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; data byte is ready
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LDA [SPI_RX]
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STA [BUF, X]
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INCX
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; check for max number of bytes reached, high byte first
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BSTX [NUMBYTES]
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LDA [MAXBYTES]
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CMPA [NUMBYTES]
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JC [LOOP] ; not yet reached
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JNZ [DONE]
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; high bytes are equal => compare low bytes as well
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LDA [MAXBYTES+1]
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CMP [NUMBYTES+1]
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JC [LOOP] ; not yet reached
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; we are done now, transfer of desired number of bytes is completed
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DONE: LDA SPI_NOP
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STA [SPI_CMD] ; write the pseudo "NOP" cmd to reset
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; the SPI controller to idle state
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Remarks:
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--------
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The flash utilizes a 3 byte address (using 20 bits for the 8Mbit
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M25P80 chip). The highest byte specifies the sector on which the PP, SE,
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johannesha |
RD, F_RD commands operate. In the DIY Calculator we use only the topmost
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sector (no. 0x0F).
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johannesha |
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The PP, RD, and F_RD commands are special in that that the number of bytes
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to be transferred is not known in advance. Therefore the dummy "NOP" command
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must be issued to the SPI Flash controller after all bytes are transferred
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to terminate the active command and return the SPI Flash controller to its
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idle state.
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For commands that expect a response (read commands) it is necessary to poll
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the SPI controller status register (address $F019) to see when the data has
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arrived.
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