URL https://opencores.org/ocsvn/spiflashcontroller/spiflashcontroller/trunk

Subversion Repositories spiflashcontroller

[/] [spiflashcontroller/] [trunk/] [spi_ctrl.vhd] - Blame information for rev 7

Details | Compare with Previous | View Log


--
-- Copyright (C) 2006 Johannes Hausensteiner (johannes.hausensteiner@pcl.at)
-- 
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
-- 
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
-- 
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
--
-- 
-- Filename: spi_ctrl.vhd
--
-- Function: SPI Flash controller for DIY Calculator
-- 
--
-- Changelog
--
--  0.1  25.Sep.2006   JH   new
--  0.2  15.Nov.2006   JH   remove old code
--  1.0   5.Feb.2007   JH   new clocking scheme
--  1.1   4.Apr.2007   JH   implement high address byte
--  1.2  16.Apr.2007   JH   clock enable
--  1.3  23.Apr.2007   JH   remove all asynchronous elements
--  1.4   4.May 2007   JH   resolve read timing
--  1.5  10.May 2007   JH   remove read signal
--
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity spi_ctrl is
  port (
    clk_in   : in std_logic;
    rst      : in std_logic;
    spi_clk  : out std_logic;
    spi_cs   : out std_logic;
    spi_din  : in std_logic;
    spi_dout : out std_logic;
    sel      : in std_logic;
    wr       : in std_logic;
    addr     : in std_logic_vector (2 downto 0);
    d_in     : in std_logic_vector (7 downto 0);
    d_out    : out std_logic_vector (7 downto 0)
  );
end spi_ctrl;
 
architecture rtl of spi_ctrl is
  -- clock generator
  constant SYS_FREQ  : integer :=  25000000;  -- 25MHz
  constant SPI_FREQ  : integer :=   6250000;  -- 6.25MHz
  signal clk_en : std_logic;
  signal clk_cnt : integer range 0 to (SYS_FREQ/SPI_FREQ)-1;
 
  type state_t is (
    IDLE, TxCMD, TxADD_H, TxADD_M, TxADD_L, TxDUMMY, TxDATA, RxDATA,
    WAIT1, WAIT2, WAIT3, WAIT4, WAIT6, WAIT5, WAIT7, WAIT8, CLR_CMD);
  signal state, next_state : state_t;
 
  -- transmitter
  signal tx_reg, tx_sreg : std_logic_vector (7 downto 0);
  signal tx_empty, tx_empty_set : std_logic;
  signal tx_bit_cnt : std_logic_vector (3 downto 0);
 
  -- receiver
  signal rx_sreg : std_logic_vector (7 downto 0);
  signal rx_ready, rx_ready_set, rx_bit_cnt_clr : std_logic;
  signal rx_bit_cnt : std_logic_vector (3 downto 0);
 
  signal wr_cmd, wr_data, wr_add_h, wr_add_m, wr_add_l : std_logic;
  signal rd_stat, rd_add_h, rd_add_m, rd_add_l : std_logic;
  signal rd_data, rd_data1, rd_data2 : std_logic;
  signal spi_cs_int, spi_clk_int : std_logic;
 
  -- auxiliary signals
  signal rx_enable, rx_empty, rx_empty_clr : std_logic;
  signal tx_enable, tx_enable_d : std_logic;
  signal tx_new_data, tx_new_data_clr, is_tx_data, is_wait6 : std_logic;
  signal cmd_clr, busy : std_logic;
 
  -- registers
  signal cmd, tx_data, rx_data : std_logic_vector (7 downto 0);
  signal add_h, add_m, add_l : std_logic_vector (7 downto 0);
 
  -- FLASH commands
  constant NOP  : std_logic_vector (7 downto 0) := x"FF";  -- no cmd to execute
  constant WREN : std_logic_vector (7 downto 0) := x"06";  -- write enable
  constant WRDI : std_logic_vector (7 downto 0) := x"04";  -- write disable
  constant RDSR : std_logic_vector (7 downto 0) := x"05";  -- read status reg
  constant WRSR : std_logic_vector (7 downto 0) := x"01";  -- write stat. reg
  constant RDCMD: std_logic_vector (7 downto 0) := x"03";  -- read data
  constant F_RD : std_logic_vector (7 downto 0) := x"0B";  -- fast read data
  constant PP :   std_logic_vector (7 downto 0) := x"02";  -- page program
  constant SE :   std_logic_vector (7 downto 0) := x"D8";  -- sector erase
  constant BE :   std_logic_vector (7 downto 0) := x"C7";  -- bulk erase
  constant DP :   std_logic_vector (7 downto 0) := x"B9";  -- deep power down
  constant RES :  std_logic_vector (7 downto 0) := x"AB";  -- read signature
begin
  -- assign signals
  spi_cs <= spi_cs_int;
  spi_clk <= spi_clk_int;
  spi_dout <= tx_sreg(7);
 
  -- clock generator
  spi_divider : process (rst, clk_in)
    begin
    if rst = '1' then
      clk_cnt <= 0;
      clk_en <= '0';
      spi_clk_int <= '1';
    elsif falling_edge (clk_in) then
      if clk_cnt = ((SYS_FREQ / SPI_FREQ) - 2) or
         clk_cnt = ((SYS_FREQ / SPI_FREQ) - 3) then
        clk_cnt <= clk_cnt + 1;
        clk_en <= '0';
        if tx_enable = '1' or rx_enable = '1' then
          spi_clk_int <= '0';
        else
          spi_clk_int <= '1';
        end if;
      elsif clk_cnt = ((SYS_FREQ / SPI_FREQ) - 1) then
        clk_cnt <= 0;
        clk_en <= '1';
        spi_clk_int <= '1';
      else
        clk_cnt <= clk_cnt + 1;
        clk_en <= '0';
        spi_clk_int <= '1';
      end if;
    end if;
  end process;
 
  -- address decoder
  process (sel, addr, wr)
    variable input : std_logic_vector (4 downto 0);
  begin
    input := sel & addr & wr;
    -- defaults
    wr_data <= '0';
    wr_cmd <= '0';
    wr_add_h <= '0';
    wr_add_m <= '0';
    wr_add_l <= '0';
    rd_data <= '0';
    rd_stat <= '0';
    rd_add_h <= '0';
    rd_add_m <= '0';
    rd_add_l <= '0';
    case input is
      when "10000" => rd_data  <= '1';
      when "10001" => wr_data  <= '1';
      when "10010" => rd_stat  <= '1';
      when "10011" => wr_cmd   <= '1';
      when "10100" => rd_add_l <= '1';
      when "10101" => wr_add_l <= '1';
      when "10110" => rd_add_m <= '1';
      when "10111" => wr_add_m <= '1';
      when "11000" => rd_add_h <= '1';
      when "11001" => wr_add_h <= '1';
      when others => null;
    end case;
  end process;
 
  -- read back registers
  d_out(0) <=    (rx_data(0) and rd_data)
              or (busy       and rd_stat)
              or (add_h(0)   and rd_add_h)
              or (add_m(0)   and rd_add_m)
              or (add_l(0)   and rd_add_l);
 
  d_out(1) <=    (rx_data(1) and rd_data)
              or (tx_empty   and rd_stat)
              or (add_h(1)   and rd_add_h)
              or (add_m(1)   and rd_add_m)
              or (add_l(1)   and rd_add_l);
 
  d_out(2) <=    (rx_data(2) and rd_data)
              or (rx_ready   and rd_stat)
              or (add_h(2)   and rd_add_h)
              or (add_m(2)   and rd_add_m)
              or (add_l(2)   and rd_add_l);
 
  d_out(3) <=    (rx_data(3) and rd_data)
              or (is_wait6   and rd_stat)
              or (add_h(3)   and rd_add_h)
              or (add_m(3)   and rd_add_m)
              or (add_l(3)   and rd_add_l);
 
  d_out(4) <=    (rx_data(4) and rd_data)
              or ('0'        and rd_stat)
              or (add_h(4)   and rd_add_h)
              or (add_m(4)   and rd_add_m)
              or (add_l(4)   and rd_add_l);
 
  d_out(5) <=    (rx_data(5) and rd_data)
              or ('0'        and rd_stat)
              or (add_h(5)   and rd_add_h)
              or (add_m(5)   and rd_add_m)
              or (add_l(5)   and rd_add_l);
 
  d_out(6) <=    (rx_data(6) and rd_data)
              or ('0'        and rd_stat)
              or (add_h(6)   and rd_add_h)
              or (add_m(6)   and rd_add_m)
              or (add_l(6)   and rd_add_l);
 
  d_out(7) <=    (rx_data(7) and rd_data)
              or ('0'        and rd_stat)
              or (add_h(7)   and rd_add_h)
              or (add_m(7)   and rd_add_m)
              or (add_l(7)   and rd_add_l);
 
  -- write command register
  process (rst, cmd_clr, clk_in)
  begin
    if rst = '1' or cmd_clr = '1' then
      cmd <= NOP;
    elsif rising_edge (clk_in) then
      if wr_cmd = '1' then
        cmd <= d_in;
      end if;
    end if;
  end process;
 
  -- write address high register
  process (rst, clk_in)
  begin
    if rst = '1' then
      add_h <= x"00";
    elsif rising_edge (clk_in) then
      if wr_add_h = '1' then
        add_h <= d_in;
      end if;
    end if;
  end process;
 
  -- write address mid register
  process (rst, clk_in)
  begin
    if rst = '1' then
      add_m <= x"00";
    elsif rising_edge (clk_in) then
      if wr_add_m ='1' then
        add_m <= d_in;
      end if;
    end if;
  end process;
 
  -- write address low register
  process (rst, clk_in)
  begin
    if rst = '1' then
      add_l <= x"00";
    elsif rising_edge (clk_in) then
      if wr_add_l ='1' then
        add_l <= d_in;
      end if;
    end if;
  end process;
 
  -- write tx data register
  process (rst, clk_in)
  begin
    if rst = '1' then
      tx_data <= x"00";
    elsif rising_edge (clk_in) then
      if wr_data = '1' then
        tx_data <= d_in;
      end if;
    end if;
  end process;
 
  -- new tx data flag
  tx_new_data_clr <= tx_empty_set and is_tx_data;
  process (rst, tx_new_data_clr, clk_in)
  begin
    if rst = '1' or tx_new_data_clr = '1' then
      tx_new_data <= '0';
    elsif rising_edge (clk_in) then
      if wr_data ='1' then
        tx_new_data <= '1';
      end if;
    end if;
  end process;
 
  -- advance the state machine
  process (rst, clk_in)
  begin
    if rst = '1' then
      state <= IDLE;
    elsif rising_edge (clk_in) then
      if clk_en = '1' then
        state <= next_state;
      end if;
    end if;
  end process;
 
  -- state machine transition table
  process (state, cmd, tx_bit_cnt, tx_new_data, rx_bit_cnt, rx_empty)
  begin
    case state is
      when IDLE =>
        case cmd is
          when NOP => next_state <= IDLE;
          when others => next_state <= TxCMD;
        end case;
 
      when TxCMD =>
        if tx_bit_cnt < x"7" then
          next_state <= TxCMD;
        else
          case cmd is
            when WREN | WRDI | BE | DP => next_state <= CLR_CMD;
            when SE | PP | RES | RDCMD | F_RD|WRSR|RDSR => next_state <= WAIT1;
            when others => next_state <= CLR_CMD;
          end case;
        end if;
 
      when WAIT1 =>
        case cmd is
          when WREN | WRDI | BE | DP => next_state <= CLR_CMD;
          when SE | PP | RES | RDCMD | F_RD => next_state <= TxADD_H;
          when WRSR => next_state <= TxDATA;
          when RDSR => next_state <= RxDATA;
          when others => next_state <= CLR_CMD;
        end case;
 
      when TxADD_H =>
        if tx_bit_cnt < x"7" then
          next_state <= TxADD_H;
        else
          next_state <= WAIT2;
        end if;
 
      when WAIT2 => next_state <= TxADD_M;
 
      when TxADD_M =>
        if tx_bit_cnt < x"7" then
          next_state <= TxADD_M;
        else
          next_state <= WAIT3;
        end if;
 
      when WAIT3 => next_state <= TxADD_L;
 
      when TxADD_L =>
        if tx_bit_cnt < x"7" then
          next_state <= TxADD_L;
        else
          case cmd is
            when PP => next_state <= WAIT6;
            when SE | RES | RDCMD | F_RD => next_state <= WAIT4;
            when others => next_state <= CLR_CMD;
          end case;
        end if;
 
      when WAIT4 =>
        case cmd is
          when F_RD => next_state <= TxDUMMY;
          when RES | RDCMD => next_state <= RxDATA;
          when others => next_state <= CLR_CMD;
        end case;
 
      when TxDUMMY =>
        if tx_bit_cnt < x"7" then
          next_state <= TxDUMMY;
        else
          next_state <= WAIT8;
        end if;
 
      when WAIT7 => next_state <= WAIT8;
 
      when WAIT8 =>
        case cmd is
          when RDCMD | F_RD =>
            if rx_empty = '1' then
              next_state <= RxDATA;
            else
              next_state <= WAIT8;
            end if;
          when others => next_state <= CLR_CMD;
        end case;
 
      when RxDATA =>
        if rx_bit_cnt < x"7" then
          next_state <= RxDATA;
        else
          case cmd is
            when RDCMD | F_RD => next_state <= WAIT7;
            when RDSR | RES => next_state <= WAIT5;
            when others => next_state <= CLR_CMD;
          end case;
        end if;
 
      when TxDATA =>
        if tx_bit_cnt < x"7" then
          next_state <= TxDATA;
        else
          case cmd is
            when PP => next_state <= WAIT6;
            when others => next_state <= CLR_CMD;
          end case;
        end if;
 
      when WAIT6 =>
        case cmd is
          when PP =>
            if tx_new_data = '1' then
              next_state <= TxDATA;
            else
              next_state <= WAIT6;
            end if;
          when others => next_state <= CLR_CMD;
        end case;
 
      when WAIT5 => next_state <= CLR_CMD;
 
      when CLR_CMD => next_state <= IDLE;
    end case;
  end process;
 
  -- state machine output table
  process (state, cmd, tx_data, add_m, add_l, add_h)
  begin
    -- default values
    tx_enable <= '0';
    rx_enable <= '0';
    rx_bit_cnt_clr <= '1';
    tx_reg <= x"FF";
    spi_cs_int <= '0';
    busy <= '1';
    cmd_clr <= '0';
    is_tx_data <= '0';
    is_wait6 <= '0';
 
    case state is
      when IDLE =>
        busy <= '0';
      when TxCMD =>
        tx_reg <= cmd;
        tx_enable <= '1';
        spi_cs_int <= '1';
      when TxDATA =>
        tx_reg <= tx_data;
        tx_enable <= '1';
        spi_cs_int <= '1';
        is_tx_data <= '1';
      when TxADD_H =>
        tx_reg <= add_h;
        tx_enable <= '1';
        spi_cs_int <= '1';
      when TxADD_M =>
        tx_reg <= add_m;
        tx_enable <= '1';
        spi_cs_int <= '1';
      when TxADD_L =>
        tx_reg <= add_l;
        tx_enable <= '1';
        spi_cs_int <= '1';
      when TxDUMMY =>
        tx_reg <= x"00";
        tx_enable <= '1';
        spi_cs_int <= '1';
      when RxDATA =>
        rx_bit_cnt_clr <= '0';
        rx_enable <= '1';
        spi_cs_int <= '1';
      when WAIT1 | WAIT2 | WAIT3 | WAIT4 | WAIT8 =>
        spi_cs_int <= '1';
      when WAIT6 =>
        is_wait6 <= '1';
        spi_cs_int <= '1';
      when WAIT5 | WAIT7 =>
        rx_bit_cnt_clr <= '0';
        spi_cs_int <= '1';
      when CLR_CMD =>
        cmd_clr <= '1';
      when others => null;
    end case;
  end process;
 
  -- the tx_empty flip flop
  process (rst, wr_data, clk_in)
  begin
    if rst = '1' then
      tx_empty <= '1';
    elsif wr_data = '1' then
      tx_empty <= '0';
    elsif rising_edge (clk_in) then
      if tx_empty_set = '1' then
        tx_empty <= '1';
      end if;
    end if;
  end process;
 
  -- delay the tx_enable signal
  process (rst, clk_in)
  begin
    if rst = '1' then
      tx_enable_d <= '0';
    elsif rising_edge (clk_in) then
      tx_enable_d <= tx_enable;
    end if;
  end process;
 
  -- transmitter shift register and bit counter
  process (rst, tx_reg, tx_enable_d, clk_in)
  begin
    if rst = '1' then
      tx_sreg <= x"FF";
      tx_bit_cnt <= x"0";
      tx_empty_set <= '0';
    elsif tx_enable_d = '0' then
      tx_sreg <= tx_reg;
      tx_bit_cnt <= x"0";
      tx_empty_set <= '0';
    elsif rising_edge (clk_in) then
      if clk_en = '1' then
        tx_bit_cnt <= tx_bit_cnt + 1;
        tx_sreg <= tx_sreg (6 downto 0) & '1';
        if tx_bit_cnt = x"6" and is_tx_data = '1' then
          tx_empty_set <= '1';
        else
          tx_empty_set <= '0';
        end if;
      end if;
    end if;
  end process;
 
  -- synchronize rd_data
  process (rst, clk_in)
  begin
    if rst = '1' then
      rd_data1 <= '0';
    elsif falling_edge (clk_in) then
      rd_data1 <= rd_data;
    end if;
  end process;
 
  process (rst, clk_in)
  begin
    if rst = '1' then
      rd_data2 <= '0';
    elsif falling_edge (clk_in) then
      if rd_data = '0' then
        rd_data2 <= rd_data1;
      end if;
    end if;
  end process;
 
  -- the rx_empty flip flop
  process (rst, clk_in)
  begin
    if rst = '1' then
      rx_empty <= '1';
    elsif rising_edge (clk_in) then
      if rx_empty_clr = '1' then
        rx_empty <= '0';
      elsif rd_data2 = '1' then
        rx_empty <= '1';
      end if;
    end if;
  end process;
 
  -- the rx_ready flip flop
  process (rst, clk_in)
  begin
    if rst = '1' then
      rx_ready <= '0';
    elsif rising_edge (clk_in) then
      if rd_data = '1' then
        rx_ready <= '0';
      elsif rx_ready_set = '1' then
        rx_ready <= '1';
      end if;
    end if;
  end process;
 
  -- the rx_data register
  process (rst, clk_in)
  begin
    if rst = '1' then
      rx_data <= x"FF";
    elsif rising_edge (clk_in) then
      if rx_ready_set = '1' then
        rx_data <= rx_sreg;
      end if;
    end if;
  end process;
 
  -- receiver shift register and bit counter
  process (rst, rx_bit_cnt_clr, clk_in)
  begin
    if rst = '1' or rx_bit_cnt_clr = '1' then
      rx_bit_cnt <= x"0";
      rx_ready_set <= '0';
      rx_empty_clr <= '0';
      rx_sreg <= x"FF";
    elsif rising_edge (clk_in) then
      if clk_en = '1' then
        rx_sreg <= rx_sreg (6 downto 0) & spi_din;
        case rx_bit_cnt is
          when x"0" =>
            rx_bit_cnt <= rx_bit_cnt + 1;
            rx_ready_set <= '0';
            rx_empty_clr <= '1';
          when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" =>
            rx_bit_cnt <= rx_bit_cnt + 1;
            rx_ready_set <= '0';
            rx_empty_clr <= '0';
          when x"7" =>
            rx_bit_cnt <= rx_bit_cnt + 1;
            rx_ready_set <= '1';
            rx_empty_clr <= '0';
          when others =>
            null;
        end case;
      end if;
    end if;
  end process;
end rtl;

Line No.	Rev	Author	Line
1	6	johannesha	`--`
2	2	johannesha	`-- Copyright (C) 2006 Johannes Hausensteiner (johannes.hausensteiner@pcl.at)`
3			`--`
4			`-- This program is free software; you can redistribute it and/or`
5			`-- modify it under the terms of the GNU General Public License`
6			`-- as published by the Free Software Foundation; either version 2`
7			`-- of the License, or (at your option) any later version.`
8			`--`
9			`-- This program is distributed in the hope that it will be useful,`
10			`-- but WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
12			`-- GNU General Public License for more details.`
13			`--`
14			`-- You should have received a copy of the GNU General Public License`
15			`-- along with this program; if not, write to the Free Software`
16			`-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.`
17			`--`
18			`--`
19			`-- Filename: spi_ctrl.vhd`
20			`--`
21			`-- Function: SPI Flash controller for DIY Calculator`
22			`--`
23			`--`
24			`-- Changelog`
25			`--`
26			`-- 0.1 25.Sep.2006 JH new`
27	6	johannesha	`-- 0.2 15.Nov.2006 JH remove old code`
28			`-- 1.0 5.Feb.2007 JH new clocking scheme`
29			`-- 1.1 4.Apr.2007 JH implement high address byte`
30			`-- 1.2 16.Apr.2007 JH clock enable`
31			`-- 1.3 23.Apr.2007 JH remove all asynchronous elements`
32			`-- 1.4 4.May 2007 JH resolve read timing`
33			`-- 1.5 10.May 2007 JH remove read signal`
34	2	johannesha	`--`
35
36
37			`library ieee;`
38			`use ieee.std_logic_1164.all;`
39			`use ieee.std_logic_unsigned.all;`
40
41			`entity spi_ctrl is`
42			`port (`
43	6	johannesha	`clk_in : in std_logic;`
44	2	johannesha	`rst : in std_logic;`
45			`spi_clk : out std_logic;`
46			`spi_cs : out std_logic;`
47			`spi_din : in std_logic;`
48			`spi_dout : out std_logic;`
49			`sel : in std_logic;`
50	6	johannesha	`wr : in std_logic;`
51			`addr : in std_logic_vector (2 downto 0);`
52	2	johannesha	`d_in : in std_logic_vector (7 downto 0);`
53			`d_out : out std_logic_vector (7 downto 0)`
54			`);`
55			`end spi_ctrl;`
56
57			`architecture rtl of spi_ctrl is`
58	6	johannesha	`-- clock generator`
59			`constant SYS_FREQ : integer := 25000000; -- 25MHz`
60			`constant SPI_FREQ : integer := 6250000; -- 6.25MHz`
61			`signal clk_en : std_logic;`
62			`signal clk_cnt : integer range 0 to (SYS_FREQ/SPI_FREQ)-1;`
63
64	2	johannesha	`type state_t is (`
65			`IDLE, TxCMD, TxADD_H, TxADD_M, TxADD_L, TxDUMMY, TxDATA, RxDATA,`
66			`WAIT1, WAIT2, WAIT3, WAIT4, WAIT6, WAIT5, WAIT7, WAIT8, CLR_CMD);`
67			`signal state, next_state : state_t;`
68
69			`-- transmitter`
70			`signal tx_reg, tx_sreg : std_logic_vector (7 downto 0);`
71			`signal tx_empty, tx_empty_set : std_logic;`
72			`signal tx_bit_cnt : std_logic_vector (3 downto 0);`
73
74			`-- receiver`
75			`signal rx_sreg : std_logic_vector (7 downto 0);`
76	6	johannesha	`signal rx_ready, rx_ready_set, rx_bit_cnt_clr : std_logic;`
77	2	johannesha	`signal rx_bit_cnt : std_logic_vector (3 downto 0);`
78
79	6	johannesha	`signal wr_cmd, wr_data, wr_add_h, wr_add_m, wr_add_l : std_logic;`
80			`signal rd_stat, rd_add_h, rd_add_m, rd_add_l : std_logic;`
81	2	johannesha	`signal rd_data, rd_data1, rd_data2 : std_logic;`
82	6	johannesha	`signal spi_cs_int, spi_clk_int : std_logic;`
83	2	johannesha
84			`-- auxiliary signals`
85			`signal rx_enable, rx_empty, rx_empty_clr : std_logic;`
86			`signal tx_enable, tx_enable_d : std_logic;`
87			`signal tx_new_data, tx_new_data_clr, is_tx_data, is_wait6 : std_logic;`
88			`signal cmd_clr, busy : std_logic;`
89
90			`-- registers`
91	6	johannesha	`signal cmd, tx_data, rx_data : std_logic_vector (7 downto 0);`
92			`signal add_h, add_m, add_l : std_logic_vector (7 downto 0);`
93	2	johannesha
94			`-- FLASH commands`
95			`constant NOP : std_logic_vector (7 downto 0) := x"FF"; -- no cmd to execute`
96			`constant WREN : std_logic_vector (7 downto 0) := x"06"; -- write enable`
97			`constant WRDI : std_logic_vector (7 downto 0) := x"04"; -- write disable`
98			`constant RDSR : std_logic_vector (7 downto 0) := x"05"; -- read status reg`
99			`constant WRSR : std_logic_vector (7 downto 0) := x"01"; -- write stat. reg`
100	6	johannesha	`constant RDCMD: std_logic_vector (7 downto 0) := x"03"; -- read data`
101	2	johannesha	`constant F_RD : std_logic_vector (7 downto 0) := x"0B"; -- fast read data`
102			`constant PP : std_logic_vector (7 downto 0) := x"02"; -- page program`
103			`constant SE : std_logic_vector (7 downto 0) := x"D8"; -- sector erase`
104			`constant BE : std_logic_vector (7 downto 0) := x"C7"; -- bulk erase`
105			`constant DP : std_logic_vector (7 downto 0) := x"B9"; -- deep power down`
106			`constant RES : std_logic_vector (7 downto 0) := x"AB"; -- read signature`
107			`begin`
108			`-- assign signals`
109			`spi_cs <= spi_cs_int;`
110	6	johannesha	`spi_clk <= spi_clk_int;`
111	2	johannesha	`spi_dout <= tx_sreg(7);`
112
113	6	johannesha	`-- clock generator`
114			`spi_divider : process (rst, clk_in)`
115			`begin`
116			`if rst = '1' then`
117			`clk_cnt <= 0;`
118			`clk_en <= '0';`
119			`spi_clk_int <= '1';`
120			`elsif falling_edge (clk_in) then`
121			`if clk_cnt = ((SYS_FREQ / SPI_FREQ) - 2) or`
122			`clk_cnt = ((SYS_FREQ / SPI_FREQ) - 3) then`
123			`clk_cnt <= clk_cnt + 1;`
124			`clk_en <= '0';`
125			`if tx_enable = '1' or rx_enable = '1' then`
126			`spi_clk_int <= '0';`
127			`else`
128			`spi_clk_int <= '1';`
129			`end if;`
130			`elsif clk_cnt = ((SYS_FREQ / SPI_FREQ) - 1) then`
131			`clk_cnt <= 0;`
132			`clk_en <= '1';`
133			`spi_clk_int <= '1';`
134			`else`
135			`clk_cnt <= clk_cnt + 1;`
136			`clk_en <= '0';`
137			`spi_clk_int <= '1';`
138			`end if;`
139			`end if;`
140			`end process;`
141
142	2	johannesha	`-- address decoder`
143	6	johannesha	`process (sel, addr, wr)`
144			`variable input : std_logic_vector (4 downto 0);`
145	2	johannesha	`begin`
146	6	johannesha	`input := sel & addr & wr;`
147	2	johannesha	`-- defaults`
148			`wr_data <= '0';`
149			`wr_cmd <= '0';`
150	6	johannesha	`wr_add_h <= '0';`
151	2	johannesha	`wr_add_m <= '0';`
152			`wr_add_l <= '0';`
153			`rd_data <= '0';`
154			`rd_stat <= '0';`
155	6	johannesha	`rd_add_h <= '0';`
156	2	johannesha	`rd_add_m <= '0';`
157			`rd_add_l <= '0';`
158			`case input is`
159	6	johannesha	`when "10000" => rd_data <= '1';`
160			`when "10001" => wr_data <= '1';`
161			`when "10010" => rd_stat <= '1';`
162			`when "10011" => wr_cmd <= '1';`
163			`when "10100" => rd_add_l <= '1';`
164			`when "10101" => wr_add_l <= '1';`
165			`when "10110" => rd_add_m <= '1';`
166			`when "10111" => wr_add_m <= '1';`
167			`when "11000" => rd_add_h <= '1';`
168			`when "11001" => wr_add_h <= '1';`
169	2	johannesha	`when others => null;`
170			`end case;`
171			`end process;`
172
173			`-- read back registers`
174			`d_out(0) <= (rx_data(0) and rd_data)`
175			`or (busy and rd_stat)`
176	6	johannesha	`or (add_h(0) and rd_add_h)`
177	2	johannesha	`or (add_m(0) and rd_add_m)`
178			`or (add_l(0) and rd_add_l);`
179
180			`d_out(1) <= (rx_data(1) and rd_data)`
181			`or (tx_empty and rd_stat)`
182	6	johannesha	`or (add_h(1) and rd_add_h)`
183	2	johannesha	`or (add_m(1) and rd_add_m)`
184			`or (add_l(1) and rd_add_l);`
185
186			`d_out(2) <= (rx_data(2) and rd_data)`
187			`or (rx_ready and rd_stat)`
188	6	johannesha	`or (add_h(2) and rd_add_h)`
189	2	johannesha	`or (add_m(2) and rd_add_m)`
190			`or (add_l(2) and rd_add_l);`
191
192			`d_out(3) <= (rx_data(3) and rd_data)`
193			`or (is_wait6 and rd_stat)`
194	6	johannesha	`or (add_h(3) and rd_add_h)`
195	2	johannesha	`or (add_m(3) and rd_add_m)`
196			`or (add_l(3) and rd_add_l);`
197
198			`d_out(4) <= (rx_data(4) and rd_data)`
199			`or ('0' and rd_stat)`
200	6	johannesha	`or (add_h(4) and rd_add_h)`
201	2	johannesha	`or (add_m(4) and rd_add_m)`
202			`or (add_l(4) and rd_add_l);`
203
204			`d_out(5) <= (rx_data(5) and rd_data)`
205			`or ('0' and rd_stat)`
206	6	johannesha	`or (add_h(5) and rd_add_h)`
207	2	johannesha	`or (add_m(5) and rd_add_m)`
208			`or (add_l(5) and rd_add_l);`
209
210			`d_out(6) <= (rx_data(6) and rd_data)`
211			`or ('0' and rd_stat)`
212	6	johannesha	`or (add_h(6) and rd_add_h)`
213	2	johannesha	`or (add_m(6) and rd_add_m)`
214			`or (add_l(6) and rd_add_l);`
215
216			`d_out(7) <= (rx_data(7) and rd_data)`
217			`or ('0' and rd_stat)`
218	6	johannesha	`or (add_h(7) and rd_add_h)`
219	2	johannesha	`or (add_m(7) and rd_add_m)`
220			`or (add_l(7) and rd_add_l);`
221
222			`-- write command register`
223	6	johannesha	`process (rst, cmd_clr, clk_in)`
224	2	johannesha	`begin`
225			`if rst = '1' or cmd_clr = '1' then`
226			`cmd <= NOP;`
227	6	johannesha	`elsif rising_edge (clk_in) then`
228			`if wr_cmd = '1' then`
229			`cmd <= d_in;`
230			`end if;`
231	2	johannesha	`end if;`
232			`end process;`
233
234	6	johannesha	`-- write address high register`
235			`process (rst, clk_in)`
236			`begin`
237			`if rst = '1' then`
238			`add_h <= x"00";`
239			`elsif rising_edge (clk_in) then`
240			`if wr_add_h = '1' then`
241			`add_h <= d_in;`
242			`end if;`
243			`end if;`
244			`end process;`
245
246	2	johannesha	`-- write address mid register`
247	6	johannesha	`process (rst, clk_in)`
248	2	johannesha	`begin`
249			`if rst = '1' then`
250			`add_m <= x"00";`
251	6	johannesha	`elsif rising_edge (clk_in) then`
252			`if wr_add_m ='1' then`
253			`add_m <= d_in;`
254			`end if;`
255	2	johannesha	`end if;`
256			`end process;`
257
258			`-- write address low register`
259	6	johannesha	`process (rst, clk_in)`
260	2	johannesha	`begin`
261			`if rst = '1' then`
262			`add_l <= x"00";`
263	6	johannesha	`elsif rising_edge (clk_in) then`
264			`if wr_add_l ='1' then`
265			`add_l <= d_in;`
266			`end if;`
267	2	johannesha	`end if;`
268			`end process;`
269
270			`-- write tx data register`
271	6	johannesha	`process (rst, clk_in)`
272	2	johannesha	`begin`
273			`if rst = '1' then`
274			`tx_data <= x"00";`
275	6	johannesha	`elsif rising_edge (clk_in) then`
276			`if wr_data = '1' then`
277			`tx_data <= d_in;`
278			`end if;`
279	2	johannesha	`end if;`
280			`end process;`
281
282			`-- new tx data flag`
283			`tx_new_data_clr <= tx_empty_set and is_tx_data;`
284	6	johannesha	`process (rst, tx_new_data_clr, clk_in)`
285	2	johannesha	`begin`
286			`if rst = '1' or tx_new_data_clr = '1' then`
287			`tx_new_data <= '0';`
288	6	johannesha	`elsif rising_edge (clk_in) then`
289			`if wr_data ='1' then`
290			`tx_new_data <= '1';`
291			`end if;`
292	2	johannesha	`end if;`
293			`end process;`
294
295			`-- advance the state machine`
296	6	johannesha	`process (rst, clk_in)`
297	2	johannesha	`begin`
298			`if rst = '1' then`
299			`state <= IDLE;`
300	6	johannesha	`elsif rising_edge (clk_in) then`
301			`if clk_en = '1' then`
302			`state <= next_state;`
303			`end if;`
304	2	johannesha	`end if;`
305			`end process;`
306
307			`-- state machine transition table`
308			`process (state, cmd, tx_bit_cnt, tx_new_data, rx_bit_cnt, rx_empty)`
309			`begin`
310			`case state is`
311			`when IDLE =>`
312			`case cmd is`
313			`when NOP => next_state <= IDLE;`
314			`when others => next_state <= TxCMD;`
315			`end case;`
316
317			`when TxCMD =>`
318			`if tx_bit_cnt < x"7" then`
319			`next_state <= TxCMD;`
320			`else`
321	6	johannesha	`case cmd is`
322			`when WREN \| WRDI \| BE \| DP => next_state <= CLR_CMD;`
323			`when SE \| PP \| RES \| RDCMD \| F_RD\|WRSR\|RDSR => next_state <= WAIT1;`
324			`when others => next_state <= CLR_CMD;`
325			`end case;`
326	2	johannesha	`end if;`
327
328			`when WAIT1 =>`
329			`case cmd is`
330			`when WREN \| WRDI \| BE \| DP => next_state <= CLR_CMD;`
331	6	johannesha	`when SE \| PP \| RES \| RDCMD \| F_RD => next_state <= TxADD_H;`
332	2	johannesha	`when WRSR => next_state <= TxDATA;`
333			`when RDSR => next_state <= RxDATA;`
334			`when others => next_state <= CLR_CMD;`
335			`end case;`
336
337			`when TxADD_H =>`
338			`if tx_bit_cnt < x"7" then`
339			`next_state <= TxADD_H;`
340			`else`
341			`next_state <= WAIT2;`
342			`end if;`
343
344			`when WAIT2 => next_state <= TxADD_M;`
345
346			`when TxADD_M =>`
347			`if tx_bit_cnt < x"7" then`
348			`next_state <= TxADD_M;`
349			`else`
350			`next_state <= WAIT3;`
351			`end if;`
352
353			`when WAIT3 => next_state <= TxADD_L;`
354
355			`when TxADD_L =>`
356			`if tx_bit_cnt < x"7" then`
357			`next_state <= TxADD_L;`
358			`else`
359			`case cmd is`
360			`when PP => next_state <= WAIT6;`
361	6	johannesha	`when SE \| RES \| RDCMD \| F_RD => next_state <= WAIT4;`
362	2	johannesha	`when others => next_state <= CLR_CMD;`
363			`end case;`
364			`end if;`
365
366			`when WAIT4 =>`
367			`case cmd is`
368			`when F_RD => next_state <= TxDUMMY;`
369	6	johannesha	`when RES \| RDCMD => next_state <= RxDATA;`
370	2	johannesha	`when others => next_state <= CLR_CMD;`
371			`end case;`
372
373			`when TxDUMMY =>`
374			`if tx_bit_cnt < x"7" then`
375			`next_state <= TxDUMMY;`
376			`else`
377			`next_state <= WAIT8;`
378			`end if;`
379
380			`when WAIT7 => next_state <= WAIT8;`
381
382			`when WAIT8 =>`
383			`case cmd is`
384	6	johannesha	`when RDCMD \| F_RD =>`
385	2	johannesha	`if rx_empty = '1' then`
386			`next_state <= RxDATA;`
387			`else`
388			`next_state <= WAIT8;`
389			`end if;`
390			`when others => next_state <= CLR_CMD;`
391			`end case;`
392
393			`when RxDATA =>`
394			`if rx_bit_cnt < x"7" then`
395			`next_state <= RxDATA;`
396			`else`
397			`case cmd is`
398	6	johannesha	`when RDCMD \| F_RD => next_state <= WAIT7;`
399	2	johannesha	`when RDSR \| RES => next_state <= WAIT5;`
400			`when others => next_state <= CLR_CMD;`
401			`end case;`
402			`end if;`
403
404			`when TxDATA =>`
405			`if tx_bit_cnt < x"7" then`
406			`next_state <= TxDATA;`
407			`else`
408			`case cmd is`
409			`when PP => next_state <= WAIT6;`
410			`when others => next_state <= CLR_CMD;`
411			`end case;`
412			`end if;`
413
414			`when WAIT6 =>`
415			`case cmd is`
416			`when PP =>`
417			`if tx_new_data = '1' then`
418			`next_state <= TxDATA;`
419			`else`
420			`next_state <= WAIT6;`
421			`end if;`
422			`when others => next_state <= CLR_CMD;`
423			`end case;`
424
425			`when WAIT5 => next_state <= CLR_CMD;`
426
427			`when CLR_CMD => next_state <= IDLE;`
428			`end case;`
429			`end process;`
430
431			`-- state machine output table`
432	6	johannesha	`process (state, cmd, tx_data, add_m, add_l, add_h)`
433	2	johannesha	`begin`
434			`-- default values`
435			`tx_enable <= '0';`
436			`rx_enable <= '0';`
437	6	johannesha	`rx_bit_cnt_clr <= '1';`
438	2	johannesha	`tx_reg <= x"FF";`
439			`spi_cs_int <= '0';`
440			`busy <= '1';`
441			`cmd_clr <= '0';`
442			`is_tx_data <= '0';`
443			`is_wait6 <= '0';`
444
445			`case state is`
446			`when IDLE =>`
447			`busy <= '0';`
448			`when TxCMD =>`
449			`tx_reg <= cmd;`
450			`tx_enable <= '1';`
451			`spi_cs_int <= '1';`
452			`when TxDATA =>`
453			`tx_reg <= tx_data;`
454			`tx_enable <= '1';`
455			`spi_cs_int <= '1';`
456			`is_tx_data <= '1';`
457			`when TxADD_H =>`
458	6	johannesha	`tx_reg <= add_h;`
459	2	johannesha	`tx_enable <= '1';`
460			`spi_cs_int <= '1';`
461			`when TxADD_M =>`
462			`tx_reg <= add_m;`
463			`tx_enable <= '1';`
464			`spi_cs_int <= '1';`
465			`when TxADD_L =>`
466			`tx_reg <= add_l;`
467			`tx_enable <= '1';`
468			`spi_cs_int <= '1';`
469			`when TxDUMMY =>`
470			`tx_reg <= x"00";`
471			`tx_enable <= '1';`
472			`spi_cs_int <= '1';`
473			`when RxDATA =>`
474	6	johannesha	`rx_bit_cnt_clr <= '0';`
475	2	johannesha	`rx_enable <= '1';`
476			`spi_cs_int <= '1';`
477			`when WAIT1 \| WAIT2 \| WAIT3 \| WAIT4 \| WAIT8 =>`
478			`spi_cs_int <= '1';`
479			`when WAIT6 =>`
480			`is_wait6 <= '1';`
481			`spi_cs_int <= '1';`
482			`when WAIT5 \| WAIT7 =>`
483	6	johannesha	`rx_bit_cnt_clr <= '0';`
484	2	johannesha	`spi_cs_int <= '1';`
485			`when CLR_CMD =>`
486			`cmd_clr <= '1';`
487			`when others => null;`
488			`end case;`
489			`end process;`
490
491			`-- the tx_empty flip flop`
492	6	johannesha	`process (rst, wr_data, clk_in)`
493	2	johannesha	`begin`
494			`if rst = '1' then`
495			`tx_empty <= '1';`
496			`elsif wr_data = '1' then`
497			`tx_empty <= '0';`
498	6	johannesha	`elsif rising_edge (clk_in) then`
499			`if tx_empty_set = '1' then`
500			`tx_empty <= '1';`

Browse

Tools

Subversion Repositories spiflashcontroller

[/] [spiflashcontroller/] [trunk/] [spi_ctrl.vhd] - Blame information for rev 7