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[/] [spigpio/] [trunk/] [rtl/] [verilog/] [spigpio.v] - Blame information for rev 3

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// RTL program for SPI GPIO -- shift 16 bit register
 
`define         P0_OP           7'b0000000 //0x00
`define         P1_OP           7'b0000001 //0x01
`define         P2_OP           7'b0000010 //0x02
`define         P3_OP           7'b0000011 //0x03
`define         P4_OP           7'b0000100 //0x04
`define         P5_OP           7'b0000101 //0x05
`define         P6_OP           7'b0000110 //0x06
`define         P7_OP           7'b0000111 //0x07
`define         P8_OP           7'b0001000 //0x08
`define         P9_OP           7'b0001001 //0x09
 
`define         P0_P9_OP        7'b0001010 //0x0A
`define         P0_P3_OP        7'b0001011 //0x0B
`define         P4_P7_OP        7'b0001100 //0x0C
`define         P8_P9_OP        7'b0001101 //0x0D
 
`define         PO_P7_IP        7'b0001110 //0x0E       
`define         P8_P9_IP        7'b0001111 //0x0F
 
`define         RAM             7'b0010011 //0x13
 
module spigpio(clk, cs, sr_in, gpioin, gpioout, sr_out);
 
        input clk, cs;
        input sr_in;
        input [9:0] gpioin;
 
        output sr_out;
        output [9:0] gpioout;
 
        reg [9:0] gpioout;
        reg sr_out;
 
        reg [7:0] ram;
        wire [6:0] addr;
        wire [7:0] data;
        wire rw;
        reg [15:0] sr;
 
        assign rw = sr[15];
        assign addr = sr[14:8];
        assign data = sr[7:0];
 
        always@(posedge clk or posedge cs)
        begin
                if (cs == 1'b0)
                begin
                        sr_out <= sr[15];
                        sr[15:1] <= sr[14:0];
                        sr[0] <= sr_in;
                end
 
                if (cs == 1'b1)
                begin
 
                        if (rw == 1'b0)
                        begin
 
                                case (addr)
                                `P0_OP    : gpioout[0] <= data[0];
                                `P1_OP    : gpioout[1] <= data[0];
                                `P2_OP    : gpioout[2] <= data[0];
                                `P3_OP    : gpioout[3] <= data[0];
                                `P4_OP    : gpioout[4] <= data[0];
                                `P5_OP    : gpioout[5] <= data[0];
                                `P6_OP    : gpioout[6] <= data[0];
                                `P7_OP    : gpioout[7] <= data[0];
                                `P8_OP    : gpioout[8] <= data[0];
                                `P9_OP    : gpioout[9] <= data[0];
 
                                `P0_P9_OP : gpioout[9:0] <= {data[0], data[0], data[0], data[0], data[0],
                                                             data[0], data[0], data[0], data[0], data[0]};
                                `P0_P3_OP : gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
                                `P4_P7_OP : gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
                                `P8_P9_OP : gpioout[9:8] <= {data[0], data[0]};
                                `RAM      : ram[7:0] <= data[7:0];
                                endcase
                        end
 
                        if (rw == 1'b1)             // READ THE PORT LEVEL
                        begin
 
                                case (addr)
                                `P0_OP    : sr[7:0] <= {7'b0, gpioout[0]};
                                `P1_OP    : sr[7:0] <= {7'b0, gpioout[1]};
                                `P2_OP    : sr[7:0] <= {7'b0, gpioout[2]};
                                `P3_OP    : sr[7:0] <= {7'b0, gpioout[3]};
                                `P4_OP    : sr[7:0] <= {7'b0, gpioout[4]};
                                `P5_OP    : sr[7:0] <= {7'b0, gpioout[5]};
                                `P6_OP    : sr[7:0] <= {7'b0, gpioout[6]};
                                `P7_OP    : sr[7:0] <= {7'b0, gpioout[7]};
                                `P8_OP    : sr[7:0] <= {7'b0, gpioout[8]};
                                `P9_OP    : sr[7:0] <= {7'b0, gpioout[9]};
                                `P0_P9_OP : sr[7:0] <= {7'b0, gpioout[0]};
                                `P0_P3_OP : sr[7:0] <= {7'b0, gpioout[0]};
                                `P4_P7_OP : sr[7:0] <= {7'b0, gpioout[4]};
                                `P8_P9_OP : sr[7:0] <= {7'b0, gpioout[8]};
                                `PO_P7_IP : sr[7:0] <= gpioin[7:0];
                                `P8_P9_IP : sr[7:0] <= gpioin[9:8];
                                `RAM      : sr[7:0] <= ram[7:0];
                                endcase
                        end
                end
        end
endmodule

Line No.	Rev	Author	Line
1	3	siva12	`// RTL program for SPI GPIO -- shift 16 bit register`
2
3			`define P0_OP 7'b0000000 //0x00
4			`define P1_OP 7'b0000001 //0x01
5			`define P2_OP 7'b0000010 //0x02
6			`define P3_OP 7'b0000011 //0x03
7			`define P4_OP 7'b0000100 //0x04
8			`define P5_OP 7'b0000101 //0x05
9			`define P6_OP 7'b0000110 //0x06
10			`define P7_OP 7'b0000111 //0x07
11			`define P8_OP 7'b0001000 //0x08
12			`define P9_OP 7'b0001001 //0x09
13
14			`define P0_P9_OP 7'b0001010 //0x0A
15			`define P0_P3_OP 7'b0001011 //0x0B
16			`define P4_P7_OP 7'b0001100 //0x0C
17			`define P8_P9_OP 7'b0001101 //0x0D
18
19			`define PO_P7_IP 7'b0001110 //0x0E
20			`define P8_P9_IP 7'b0001111 //0x0F
21
22			`define RAM 7'b0010011 //0x13
23
24			`module spigpio(clk, cs, sr_in, gpioin, gpioout, sr_out);`
25
26			`input clk, cs;`
27			`input sr_in;`
28			`input [9:0] gpioin;`
29
30			`output sr_out;`
31			`output [9:0] gpioout;`
32
33			`reg [9:0] gpioout;`
34			`reg sr_out;`
35
36			`reg [7:0] ram;`
37			`wire [6:0] addr;`
38			`wire [7:0] data;`
39			`wire rw;`
40			`reg [15:0] sr;`
41
42			`assign rw = sr[15];`
43			`assign addr = sr[14:8];`
44			`assign data = sr[7:0];`
45
46			`always@(posedge clk or posedge cs)`
47			`begin`
48			`if (cs == 1'b0)`
49			`begin`
50			`sr_out <= sr[15];`
51			`sr[15:1] <= sr[14:0];`
52			`sr[0] <= sr_in;`
53			`end`
54
55			`if (cs == 1'b1)`
56			`begin`
57
58			`if (rw == 1'b0)`
59			`begin`
60
61			`case (addr)`
62			`P0_OP : gpioout[0] <= data[0];
63			`P1_OP : gpioout[1] <= data[0];
64			`P2_OP : gpioout[2] <= data[0];
65			`P3_OP : gpioout[3] <= data[0];
66			`P4_OP : gpioout[4] <= data[0];
67			`P5_OP : gpioout[5] <= data[0];
68			`P6_OP : gpioout[6] <= data[0];
69			`P7_OP : gpioout[7] <= data[0];
70			`P8_OP : gpioout[8] <= data[0];
71			`P9_OP : gpioout[9] <= data[0];
72
73			`P0_P9_OP : gpioout[9:0] <= {data[0], data[0], data[0], data[0], data[0],
74			`data[0], data[0], data[0], data[0], data[0]};`
75			`P0_P3_OP : gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
76			`P4_P7_OP : gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
77			`P8_P9_OP : gpioout[9:8] <= {data[0], data[0]};
78			`RAM : ram[7:0] <= data[7:0];
79			`endcase`
80			`end`
81
82			`if (rw == 1'b1) // READ THE PORT LEVEL`
83			`begin`
84
85			`case (addr)`
86			`P0_OP : sr[7:0] <= {7'b0, gpioout[0]};
87			`P1_OP : sr[7:0] <= {7'b0, gpioout[1]};
88			`P2_OP : sr[7:0] <= {7'b0, gpioout[2]};
89			`P3_OP : sr[7:0] <= {7'b0, gpioout[3]};
90			`P4_OP : sr[7:0] <= {7'b0, gpioout[4]};
91			`P5_OP : sr[7:0] <= {7'b0, gpioout[5]};
92			`P6_OP : sr[7:0] <= {7'b0, gpioout[6]};
93			`P7_OP : sr[7:0] <= {7'b0, gpioout[7]};
94			`P8_OP : sr[7:0] <= {7'b0, gpioout[8]};
95			`P9_OP : sr[7:0] <= {7'b0, gpioout[9]};
96			`P0_P9_OP : sr[7:0] <= {7'b0, gpioout[0]};
97			`P0_P3_OP : sr[7:0] <= {7'b0, gpioout[0]};
98			`P4_P7_OP : sr[7:0] <= {7'b0, gpioout[4]};
99			`P8_P9_OP : sr[7:0] <= {7'b0, gpioout[8]};
100			`PO_P7_IP : sr[7:0] <= gpioin[7:0];
101			`P8_P9_IP : sr[7:0] <= gpioin[9:8];
102			`RAM : sr[7:0] <= ram[7:0];
103			`endcase`
104			`end`
105			`end`
106			`end`
107			`endmodule`

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[/] [spigpio/] [trunk/] [rtl/] [verilog/] [spigpio.v] - Blame information for rev 3