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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// SPI GPIO IP Core                                             ////
////                                                              ////
//// This file is part of the spigpio project                     ////
//// http://www.opencores.org/project,spislave                    ////
////                                                              ////
//// Description                                                  ////
//// Implementation of spislave IP core according to              ////
//// spigpio IP core specification document.                      ////
////                                                              ////
//// To Do:                                                       ////
////   -                                                          ////
////                                                              ////
//// Author(s):                                                   ////
////      - Sivakumar.B , email: siva@zilogic.com                 ////
////                      email: siva12@opencores.org             ////
////        Engineer  Zilogic systems,chennai. www.zilogic.com    ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Zilogic Systems and OPENCORES.ORG         ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////       RTL program for SPI GPIO --                            ////  
 
`define         P0_OP           7'b0000000 //0x00
`define         P1_OP           7'b0000001 //0x01
`define         P2_OP           7'b0000010 //0x02
`define         P3_OP           7'b0000011 //0x03
`define         P4_OP           7'b0000100 //0x04
`define         P5_OP           7'b0000101 //0x05
`define         P6_OP           7'b0000110 //0x06
`define         P7_OP           7'b0000111 //0x07
`define         P8_OP           7'b0001000 //0x08
`define         P9_OP           7'b0001001 //0x09
 
`define         P0_P9_OP        7'b0001010 //0x0A
`define         P0_P3_OP        7'b0001011 //0x0B
`define         P4_P7_OP        7'b0001100 //0x0C
`define         P8_P9_OP        7'b0001101 //0x0D
 
`define         PO_P7_IP        7'b0001110 //0x0E       
`define         P8_P9_IP        7'b0001111 //0x0F
 
`define         RAM             7'b0010011 //0x13
 
module spigpio(clk, cs, sr_in, gpioin, gpioout, sr_out);
 
        input clk, cs;
        input sr_in;
        input [9:0] gpioin;
 
        output sr_out;
        output [9:0] gpioout;
 
        reg [9:0] gpioout;
        reg sr_out;
 
        reg [7:0] ram;
        wire [6:0] addr;
        wire [7:0] data;
        wire rw;
        reg [15:0] sr;
 
        assign rw = sr[15];
        assign addr = sr[14:8];
        assign data = sr[7:0];
 
        always@(posedge clk or posedge cs)
        begin
                if (cs == 1'b0)
                begin
                        sr_out <= sr[15];
                        sr[15:1] <= sr[14:0];
                        sr[0] <= sr_in;
                end
 
                if (cs == 1'b1)
                begin
 
                        if (rw == 1'b0)
                        begin
 
                                case (addr)
                                `P0_OP    : gpioout[0] <= data[0];
                                `P1_OP    : gpioout[1] <= data[0];
                                `P2_OP    : gpioout[2] <= data[0];
                                `P3_OP    : gpioout[3] <= data[0];
                                `P4_OP    : gpioout[4] <= data[0];
                                `P5_OP    : gpioout[5] <= data[0];
                                `P6_OP    : gpioout[6] <= data[0];
                                `P7_OP    : gpioout[7] <= data[0];
                                `P8_OP    : gpioout[8] <= data[0];
                                `P9_OP    : gpioout[9] <= data[0];
 
                                `P0_P9_OP : gpioout[9:0] <= {data[0], data[0], data[0], data[0], data[0],
                                                             data[0], data[0], data[0], data[0], data[0]};
                                `P0_P3_OP : gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
                                `P4_P7_OP : gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
                                `P8_P9_OP : gpioout[9:8] <= {data[0], data[0]};
                                `RAM      : ram[7:0] <= data[7:0];
                                endcase
                        end
 
                        if (rw == 1'b1)             // READ THE PORT LEVEL
                        begin
 
                                case (addr)
                                `P0_OP    : sr[7:0] <= {7'b0, gpioout[0]};
                                `P1_OP    : sr[7:0] <= {7'b0, gpioout[1]};
                                `P2_OP    : sr[7:0] <= {7'b0, gpioout[2]};
                                `P3_OP    : sr[7:0] <= {7'b0, gpioout[3]};
                                `P4_OP    : sr[7:0] <= {7'b0, gpioout[4]};
                                `P5_OP    : sr[7:0] <= {7'b0, gpioout[5]};
                                `P6_OP    : sr[7:0] <= {7'b0, gpioout[6]};
                                `P7_OP    : sr[7:0] <= {7'b0, gpioout[7]};
                                `P8_OP    : sr[7:0] <= {7'b0, gpioout[8]};
                                `P9_OP    : sr[7:0] <= {7'b0, gpioout[9]};
                                `P0_P9_OP : sr[7:0] <= {7'b0, gpioout[0]};
                                `P0_P3_OP : sr[7:0] <= {7'b0, gpioout[0]};
                                `P4_P7_OP : sr[7:0] <= {7'b0, gpioout[4]};
                                `P8_P9_OP : sr[7:0] <= {7'b0, gpioout[8]};
                                `PO_P7_IP : sr[7:0] <= gpioin[7:0];
                                `P8_P9_IP : sr[7:0] <= gpioin[9:8];
                                `RAM      : sr[7:0] <= ram[7:0];
                                endcase
                        end
                end
        end
endmodule

Line No.	Rev	Author	Line
1	4	siva12	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SPI GPIO IP Core ////`
4			`//// ////`
5			`//// This file is part of the spigpio project ////`
6			`//// http://www.opencores.org/project,spislave ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of spislave IP core according to ////`
10			`//// spigpio IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Sivakumar.B , email: siva@zilogic.com ////`
17			`//// email: siva12@opencores.org ////`
18			`//// Engineer Zilogic systems,chennai. www.zilogic.com ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//// ////`
22			`//// Copyright (C) 2009 Zilogic Systems and OPENCORES.ORG ////`
23			`//// ////`
24			`//// This source file may be used and distributed without ////`
25			`//// restriction provided that this copyright statement is not ////`
26			`//// removed from the file and that any derivative work contains ////`
27			`//// the original copyright notice and the associated disclaimer. ////`
28			`//// ////`
29			`//// This source file is free software; you can redistribute it ////`
30			`//// and/or modify it under the terms of the GNU Lesser General ////`
31			`//// Public License as published by the Free Software Foundation; ////`
32			`//// either version 2.1 of the License, or (at your option) any ////`
33			`//// later version. ////`
34			`//// ////`
35			`//// This source is distributed in the hope that it will be ////`
36			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
37			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
38			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
39			`//// details. ////`
40			`//// ////`
41			`//// You should have received a copy of the GNU Lesser General ////`
42			`//// Public License along with this source; if not, download it ////`
43			`//// from http://www.opencores.org/lgpl.shtml ////`
44			`//// ////`
45			`//////////////////////////////////////////////////////////////////////`
46	5	siva12	`//// RTL program for SPI GPIO -- ////`
47	3	siva12
48			`define P0_OP 7'b0000000 //0x00
49			`define P1_OP 7'b0000001 //0x01
50			`define P2_OP 7'b0000010 //0x02
51			`define P3_OP 7'b0000011 //0x03
52			`define P4_OP 7'b0000100 //0x04
53			`define P5_OP 7'b0000101 //0x05
54			`define P6_OP 7'b0000110 //0x06
55			`define P7_OP 7'b0000111 //0x07
56			`define P8_OP 7'b0001000 //0x08
57			`define P9_OP 7'b0001001 //0x09
58
59			`define P0_P9_OP 7'b0001010 //0x0A
60			`define P0_P3_OP 7'b0001011 //0x0B
61			`define P4_P7_OP 7'b0001100 //0x0C
62			`define P8_P9_OP 7'b0001101 //0x0D
63
64			`define PO_P7_IP 7'b0001110 //0x0E
65			`define P8_P9_IP 7'b0001111 //0x0F
66
67			`define RAM 7'b0010011 //0x13
68
69			`module spigpio(clk, cs, sr_in, gpioin, gpioout, sr_out);`
70
71			`input clk, cs;`
72			`input sr_in;`
73			`input [9:0] gpioin;`
74
75			`output sr_out;`
76			`output [9:0] gpioout;`
77
78			`reg [9:0] gpioout;`
79			`reg sr_out;`
80
81			`reg [7:0] ram;`
82			`wire [6:0] addr;`
83			`wire [7:0] data;`
84			`wire rw;`
85			`reg [15:0] sr;`
86
87			`assign rw = sr[15];`
88			`assign addr = sr[14:8];`
89			`assign data = sr[7:0];`
90
91			`always@(posedge clk or posedge cs)`
92			`begin`
93			`if (cs == 1'b0)`
94			`begin`
95			`sr_out <= sr[15];`
96			`sr[15:1] <= sr[14:0];`
97			`sr[0] <= sr_in;`
98			`end`
99
100			`if (cs == 1'b1)`
101			`begin`
102
103			`if (rw == 1'b0)`
104			`begin`
105
106			`case (addr)`
107			`P0_OP : gpioout[0] <= data[0];
108			`P1_OP : gpioout[1] <= data[0];
109			`P2_OP : gpioout[2] <= data[0];
110			`P3_OP : gpioout[3] <= data[0];
111			`P4_OP : gpioout[4] <= data[0];
112			`P5_OP : gpioout[5] <= data[0];
113			`P6_OP : gpioout[6] <= data[0];
114			`P7_OP : gpioout[7] <= data[0];
115			`P8_OP : gpioout[8] <= data[0];
116			`P9_OP : gpioout[9] <= data[0];
117
118			`P0_P9_OP : gpioout[9:0] <= {data[0], data[0], data[0], data[0], data[0],
119			`data[0], data[0], data[0], data[0], data[0]};`
120			`P0_P3_OP : gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
121			`P4_P7_OP : gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
122			`P8_P9_OP : gpioout[9:8] <= {data[0], data[0]};
123			`RAM : ram[7:0] <= data[7:0];
124			`endcase`
125			`end`
126
127			`if (rw == 1'b1) // READ THE PORT LEVEL`
128			`begin`
129
130			`case (addr)`
131			`P0_OP : sr[7:0] <= {7'b0, gpioout[0]};
132			`P1_OP : sr[7:0] <= {7'b0, gpioout[1]};
133			`P2_OP : sr[7:0] <= {7'b0, gpioout[2]};
134			`P3_OP : sr[7:0] <= {7'b0, gpioout[3]};
135			`P4_OP : sr[7:0] <= {7'b0, gpioout[4]};
136			`P5_OP : sr[7:0] <= {7'b0, gpioout[5]};
137			`P6_OP : sr[7:0] <= {7'b0, gpioout[6]};
138			`P7_OP : sr[7:0] <= {7'b0, gpioout[7]};
139			`P8_OP : sr[7:0] <= {7'b0, gpioout[8]};
140			`P9_OP : sr[7:0] <= {7'b0, gpioout[9]};
141			`P0_P9_OP : sr[7:0] <= {7'b0, gpioout[0]};
142			`P0_P3_OP : sr[7:0] <= {7'b0, gpioout[0]};
143			`P4_P7_OP : sr[7:0] <= {7'b0, gpioout[4]};
144			`P8_P9_OP : sr[7:0] <= {7'b0, gpioout[8]};
145			`PO_P7_IP : sr[7:0] <= gpioin[7:0];
146			`P8_P9_IP : sr[7:0] <= gpioin[9:8];
147			`RAM : sr[7:0] <= ram[7:0];
148			`endcase`
149			`end`
150			`end`
151			`end`
152			`endmodule`

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[/] [spigpio/] [trunk/] [rtl/] [verilog/] [spigpio.v] - Blame information for rev 5