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[/] [spimaster/] [trunk/] [RTL/] [ctrlStsRegBI.v] - Blame information for rev 4

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1 2 sfielding
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// ctrlStsRegBI.v                                               ////
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////                                                              ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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//// Wishbone bus interface to spiMaster control and status regs
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "spiMaster_defines.v"
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module ctrlStsRegBI (
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  busClk,
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  rstFromWire,
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  dataIn,
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  dataOut,
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  address,
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  writeEn,
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  strobe_i,
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  spiSysClk,
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  spiTransType,
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  spiTransCtrl,
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  spiTransStatus,
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  spiDirectAccessTxData,
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  spiDirectAccessRxData,
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  ctrlStsRegSel,
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  rstSyncToBusClkOut,
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  rstSyncToSpiClkOut,
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  SDWriteError,
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  SDReadError,
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  SDInitError,
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  SDAddr,
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  spiClkDelay
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);
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input [7:0] dataIn;
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input [7:0] address;
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input writeEn;
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input strobe_i;
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input busClk;
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input spiSysClk;
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output [7:0] dataOut;
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input ctrlStsRegSel;
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output [1:0] spiTransType;
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output spiTransCtrl;
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input spiTransStatus;
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output [7:0] spiDirectAccessTxData;
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reg [7:0] spiDirectAccessTxData;
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input [7:0] spiDirectAccessRxData;
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input rstFromWire;
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output rstSyncToBusClkOut;
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output rstSyncToSpiClkOut;
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input [1:0] SDWriteError;
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input [1:0] SDReadError;
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input [1:0] SDInitError;
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output [31:0] SDAddr;
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reg [31:0] SDAddr;
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output [7:0] spiClkDelay;
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reg [7:0] spiClkDelay;
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wire [7:0] dataIn;
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wire [7:0] address;
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wire writeEn;
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wire strobe_i;
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wire clk;
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reg [7:0] dataOut;
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reg [1:0] spiTransType;
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reg spiTransCtrl;
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wire ctrlStsRegSel;
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wire rstFromWire;
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reg rstSyncToBusClkOut;
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reg rstSyncToSpiClkOut;
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//internal wire and regs
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reg [5:0] rstShift;
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reg rstFromBus;
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reg [7:0] spiDirectAccessTxDataSTB;
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reg [7:0] spiDirectAccessRxDataSTB;
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reg [1:0] spiTransTypeSTB;
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reg spiTransCtrlSTB;
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reg spiTransStatusSTB;
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reg rstSyncToSpiClkFirst;
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reg [5:0] spiTransCtrlShift;
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reg spiTransStatusReg1;
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reg spiTransStatusReg2;
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reg spiTransStatusReg3;
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reg [1:0] SDWriteErrorSTB;
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reg [1:0] SDReadErrorSTB;
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reg [1:0] SDInitErrorSTB;
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reg spiTransCtrl_reg1;
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reg spiTransCtrl_reg2;
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reg spiTransCtrl_reg3;
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//sync write demux
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always @(posedge busClk)
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begin
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  if (rstSyncToBusClkOut == 1'b1) begin
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    spiTransTypeSTB <= `DIRECT_ACCESS;
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    spiTransCtrlSTB <= `TRANS_STOP;
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    spiDirectAccessTxDataSTB <= 8'h00;
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    spiClkDelay <= `FAST_SPI_CLK;
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  end
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  else begin
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    if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1 && address == `SPI_MASTER_CONTROL_REG && dataIn[0] == 1'b1 )
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      rstFromBus <= 1'b1;
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    else
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      rstFromBus <= 1'b0;
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    if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1 && address == `TRANS_CTRL_REG && dataIn[0] == 1'b1 )
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      spiTransCtrlSTB <= 1'b1;
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    else
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      spiTransCtrlSTB <= 1'b0;
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    if (writeEn == 1'b1 && ctrlStsRegSel == 1'b1 && strobe_i == 1'b1) begin
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      case (address)
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        `TRANS_TYPE_REG: spiTransTypeSTB <= dataIn[1:0];
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        `SD_ADDR_7_0_REG: SDAddr[7:0] <= dataIn;
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        `SD_ADDR_15_8_REG: SDAddr[15:8] <= dataIn;
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        `SD_ADDR_23_16_REG: SDAddr[23:16] <= dataIn;
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        `SD_ADDR_31_24_REG: SDAddr[31:24] <= dataIn;
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        `SPI_CLK_DEL_REG: spiClkDelay <= dataIn;
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        `DIRECT_ACCESS_DATA_REG: spiDirectAccessTxDataSTB <= dataIn;
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      endcase
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    end
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  end
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end
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// async read mux
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always @(address or spiTransTypeSTB or spiTransCtrlSTB or
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         spiTransStatusSTB or spiDirectAccessRxDataSTB or
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         SDAddr or SDInitErrorSTB or SDReadErrorSTB or SDWriteErrorSTB or
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         spiClkDelay)
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begin
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  case (address)
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    `SPI_MASTER_VERSION_REG: dataOut <= `SPI_MASTER_VERSION_NUM;
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    `TRANS_TYPE_REG: dataOut <= { 6'b000000, spiTransTypeSTB};
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    `TRANS_CTRL_REG: dataOut <= { 7'b0000000, spiTransCtrlSTB};
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    `TRANS_STS_REG: dataOut <= { 7'b0000000, spiTransStatusSTB};
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    `TRANS_ERROR_REG: dataOut <= {2'b00, SDWriteErrorSTB, SDReadErrorSTB, SDInitErrorSTB};
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    `SD_ADDR_7_0_REG: dataOut <= SDAddr[7:0];
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    `SD_ADDR_15_8_REG: dataOut <= SDAddr[15:8];
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    `SD_ADDR_23_16_REG: dataOut <= SDAddr[23:16];
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    `SD_ADDR_31_24_REG: dataOut <= SDAddr[31:24];
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    `SPI_CLK_DEL_REG: dataOut <= spiClkDelay;
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    `DIRECT_ACCESS_DATA_REG: dataOut <= spiDirectAccessRxDataSTB;
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    default: dataOut <= 8'h00;
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  endcase
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end
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// reset control
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//generate 'rstSyncToBusClk'
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//assuming that 'busClk' < 5 * 'spiSysClk'.
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always @(posedge busClk) begin
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  if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
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    rstShift <= 6'b111111;
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  else
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    rstShift <= {1'b0, rstShift[5:1]};
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end
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always @(rstShift)
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  rstSyncToBusClkOut <= rstShift[0];
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// double sync across clock domains to generate 'rstSyncToSpiClkOut'
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always @(posedge spiSysClk) begin
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    rstSyncToSpiClkFirst <= rstSyncToBusClkOut;
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    rstSyncToSpiClkOut <= rstSyncToSpiClkFirst;
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end
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// spi transaction control
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//assuming that 'busClk' < 5 * 'spiSysClk'.
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always @(posedge busClk) begin
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  if (rstSyncToBusClkOut == 1'b1)
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    spiTransCtrlShift <= 6'b000000;
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  else if (spiTransCtrlSTB == 1'b1)
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    spiTransCtrlShift <= 6'b111111;
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  else
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    spiTransCtrlShift <= {1'b0, spiTransCtrlShift[5:1]};
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end
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//re-sync to spiSysClk
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always @(posedge spiSysClk) begin
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  if (rstSyncToSpiClkOut == 1'b1) begin
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    spiTransCtrl_reg1 <= 1'b0;
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    spiTransCtrl_reg2 <= 1'b0;
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    spiTransCtrl_reg3 <= 1'b0;
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  end
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  else begin
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    spiTransCtrl_reg1 <= spiTransCtrlShift[0];
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    spiTransCtrl_reg2 <= spiTransCtrl_reg1;
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    spiTransCtrl_reg3 <= spiTransCtrl_reg2;
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    if (spiTransCtrl_reg3 == 1'b0 && spiTransCtrl_reg2 == 1'b1)
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      spiTransCtrl <= `TRANS_START;
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    else
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      spiTransCtrl <= `TRANS_STOP;
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  end
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end
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//re-sync from busClk to spiSysClk. 
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always @(posedge spiSysClk) begin
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  if (rstSyncToSpiClkOut == 1'b1) begin
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    spiTransType <= `DIRECT_ACCESS;
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    spiDirectAccessTxData <= 8'h00;
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  end
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  else begin
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    spiDirectAccessTxData <= spiDirectAccessTxDataSTB;
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    spiTransType <= spiTransTypeSTB;
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  end
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end
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//re-sync from spiSysClk to busClk
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always @(posedge busClk) begin
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  if (rstSyncToBusClkOut == 1'b1) begin
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    spiTransStatusSTB <= `TRANS_NOT_BUSY;
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    spiTransStatusReg1 <= `TRANS_NOT_BUSY;
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    spiTransStatusReg2 <= `TRANS_NOT_BUSY;
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    spiTransStatusReg3 <= `TRANS_NOT_BUSY;
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  end
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  else begin
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    spiTransStatusReg1 <= spiTransStatus;
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    spiTransStatusReg2 <= spiTransStatusReg1;
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    spiTransStatusReg3 <= spiTransStatusReg2;
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    if (spiTransCtrlSTB == `TRANS_START)
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      spiTransStatusSTB <= `TRANS_BUSY;
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    else if (spiTransStatusReg3 == `TRANS_BUSY && spiTransStatusReg2 == `TRANS_NOT_BUSY)
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      spiTransStatusSTB <= `TRANS_NOT_BUSY;
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  end
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  spiDirectAccessRxDataSTB <= spiDirectAccessRxData;
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  SDWriteErrorSTB <= SDWriteError;
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  SDReadErrorSTB <= SDReadError;
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  SDInitErrorSTB <= SDInitError;
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end
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endmodule
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