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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// readWriteSDBlock.v                             ////
////                                                              ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// If readWriteSDBlockReq equals WRITE_SD_BLOCK or
//// READ_SD_BLOCK, then write or read a 512 byte block
//// of SD memory
//// 
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "spiMaster_defines.v"
 
module readWriteSDBlock (blockAddr, checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, readError, readWriteSDBlockRdy, readWriteSDBlockReq, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, rxFifoData, rxFifoWen, sendCmdRdy, sendCmdReq, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen, txFifoData, txFifoRen, writeError);
input   [31:0]blockAddr;
input   clk;
input   [1:0]readWriteSDBlockReq;
input   [7:0]respByte;
input   respTout;
input   rst;
input   [7:0]rxDataIn;
input   rxDataRdy;
input   sendCmdRdy;
input   txDataEmpty;
input   txDataFull;
input   [7:0]txFifoData;
output  [7:0]checkSumByte;
output  [7:0]cmdByte;
output  [7:0]dataByte1;
output  [7:0]dataByte2;
output  [7:0]dataByte3;
output  [7:0]dataByte4;
output  [1:0]readError;
output  readWriteSDBlockRdy;
output  rxDataRdyClr;
output  [7:0]rxFifoData;
output  rxFifoWen;
output  sendCmdReq;
output  spiCS_n;
output  [7:0]txDataOut;
output  txDataWen;
output  txFifoRen;
output  [1:0]writeError;
 
wire    [31:0]blockAddr;
reg     [7:0]checkSumByte, next_checkSumByte;
wire    clk;
reg     [7:0]cmdByte, next_cmdByte;
reg     [7:0]dataByte1, next_dataByte1;
reg     [7:0]dataByte2, next_dataByte2;
reg     [7:0]dataByte3, next_dataByte3;
reg     [7:0]dataByte4, next_dataByte4;
reg     [1:0]readError, next_readError;
reg     readWriteSDBlockRdy, next_readWriteSDBlockRdy;
wire    [1:0]readWriteSDBlockReq;
wire    [7:0]respByte;
wire    respTout;
wire    rst;
wire    [7:0]rxDataIn;
wire    rxDataRdy;
reg     rxDataRdyClr, next_rxDataRdyClr;
reg     [7:0]rxFifoData, next_rxFifoData;
reg     rxFifoWen, next_rxFifoWen;
wire    sendCmdRdy;
reg     sendCmdReq, next_sendCmdReq;
reg     spiCS_n, next_spiCS_n;
wire    txDataEmpty;
wire    txDataFull;
reg     [7:0]txDataOut, next_txDataOut;
reg     txDataWen, next_txDataWen;
wire    [7:0]txFifoData;
reg     txFifoRen, next_txFifoRen;
reg     [1:0]writeError, next_writeError;
 
// diagram signals declarations
reg  [7:0]delCnt1, next_delCnt1;
reg  [7:0]delCnt2, next_delCnt2;
reg  [7:0]locRespByte, next_locRespByte;
reg  [8:0]loopCnt, next_loopCnt;
reg  [11:0]timeOutCnt, next_timeOutCnt;
 
// BINARY ENCODED state machine: rwBlkSt
// State codes definitions:
`define ST_RW_SD 6'b000000
`define WR_CMD_SEND_CMD 6'b000001
`define WR_CMD_WT_FIN 6'b000010
`define WR_CMD_DEL 6'b000011
`define WT_REQ 6'b000100
`define WR_TOKEN_FF1_FIN 6'b000101
`define WR_TOKEN_FF1_ST 6'b000110
`define WR_TOKEN_FF2_FIN 6'b000111
`define WR_TOKEN_FF2_ST 6'b001000
`define WR_TOKEN_FE_FIN 6'b001001
`define WR_TOKEN_FE_ST 6'b001010
`define WR_DATA_D_FIN 6'b001011
`define WR_DATA_D_ST 6'b001100
`define WR_DATA_RD_FIFO1 6'b001101
`define WR_DATA_RD_FIFO2 6'b001110
`define WR_DATA_LOOP_INIT 6'b001111
`define WR_DATA_CS_ST1 6'b010000
`define WR_DATA_CS_FIN1 6'b010001
`define WR_DATA_CS_FIN2 6'b010010
`define WR_DATA_CS_ST2 6'b010011
`define WR_DATA_CHK_RESP 6'b010100
`define WR_DATA_REQ_RESP_ST 6'b010101
`define WR_DATA_REQ_RESP_FIN 6'b010110
`define RD_CMD_SEND_CMD 6'b010111
`define RD_CMD_WT_FIN 6'b011000
`define RD_CMD_DEL 6'b011001
`define RD_TOKEN_CHK_LOOP 6'b011010
`define RD_TOKEN_WT_FIN 6'b011011
`define RD_TOKEN_SEND_CMD 6'b011100
`define RD_TOKEN_DEL2 6'b011101
`define RD_TOKEN_INIT_LOOP 6'b011110
`define RD_TOKEN_DEL1 6'b011111
`define RD_DATA_ST_LOOP 6'b100000
`define RD_DATA_WT_DATA 6'b100001
`define RD_DATA_CHK_LOOP 6'b100010
`define RD_DATA_CLR_RX 6'b100011
`define RD_DATA_CS_FIN2 6'b100100
`define RD_DATA_CS_FIN1 6'b100101
`define RD_DATA_CS_ST1 6'b100110
`define RD_DATA_CS_ST2 6'b100111
`define WR_BUSY_CHK_FIN 6'b101000
`define WR_BUSY_WT_FIN1 6'b101001
`define WR_BUSY_DEL1 6'b101010
`define WR_BUSY_SEND_CMD1 6'b101011
`define WR_BUSY_DEL2 6'b101100
`define WR_BUSY_INIT_LOOP 6'b101101
`define RD_TOKEN_DEL3 6'b101110
`define WR_DATA_DEL 6'b101111
 
reg [5:0]CurrState_rwBlkSt, NextState_rwBlkSt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
 
 
// Machine: rwBlkSt
 
// NextState logic (combinatorial)
always @ (blockAddr or sendCmdRdy or respTout or respByte or readWriteSDBlockReq or txDataFull or loopCnt or txFifoData or txDataEmpty or timeOutCnt or locRespByte or rxDataRdy or rxDataIn or delCnt1 or delCnt2 or readWriteSDBlockRdy or spiCS_n or readError or writeError or txDataOut or txDataWen or rxDataRdyClr or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or txFifoRen or rxFifoWen or rxFifoData or CurrState_rwBlkSt)
begin
  NextState_rwBlkSt <= CurrState_rwBlkSt;
  // Set default values for outputs and signals
  next_readWriteSDBlockRdy <= readWriteSDBlockRdy;
  next_spiCS_n <= spiCS_n;
  next_readError <= readError;
  next_writeError <= writeError;
  next_txDataOut <= txDataOut;
  next_txDataWen <= txDataWen;
  next_rxDataRdyClr <= rxDataRdyClr;
  next_cmdByte <= cmdByte;
  next_dataByte1 <= dataByte1;
  next_dataByte2 <= dataByte2;
  next_dataByte3 <= dataByte3;
  next_dataByte4 <= dataByte4;
  next_checkSumByte <= checkSumByte;
  next_sendCmdReq <= sendCmdReq;
  next_loopCnt <= loopCnt;
  next_delCnt1 <= delCnt1;
  next_delCnt2 <= delCnt2;
  next_txFifoRen <= txFifoRen;
  next_rxFifoWen <= rxFifoWen;
  next_rxFifoData <= rxFifoData;
  next_timeOutCnt <= timeOutCnt;
  next_locRespByte <= locRespByte;
  case (CurrState_rwBlkSt)  // synopsys parallel_case full_case
    `ST_RW_SD:
    begin
      next_readWriteSDBlockRdy <= 1'b0;
      next_spiCS_n <= 1'b1;
      next_readError <= 1'b0;
      next_writeError <= 1'b0;
      next_txDataOut <= 8'h00;
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
      next_cmdByte <= 8'h00;
      next_dataByte1 <= 8'h00;
      next_dataByte2 <= 8'h00;
      next_dataByte3 <= 8'h00;
      next_dataByte4 <= 8'h00;
      next_checkSumByte <= 8'h00;
      next_sendCmdReq <= 1'b0;
      next_loopCnt <= 8'h00;
      next_delCnt1 <= 8'h00;
      next_delCnt2 <= 8'h00;
      next_readError <= `READ_NO_ERROR;
      next_writeError <= `WRITE_NO_ERROR;
      next_txFifoRen <= 1'b0;
      next_rxFifoWen <= 1'b0;
      next_rxFifoData <= 8'h00;
      next_timeOutCnt <= 12'h000;
      next_locRespByte <= 8'h00;
      NextState_rwBlkSt <= `WT_REQ;
    end
    `WT_REQ:
    begin
      next_spiCS_n <= 1'b1;
      next_readWriteSDBlockRdy <= 1'b1;
      next_cmdByte <= 8'h00;
      next_dataByte1 <= 8'h00;
      next_dataByte2 <= 8'h00;
      next_dataByte3 <= 8'h00;
      next_dataByte4 <= 8'h00;
      next_checkSumByte <= 8'h00;
      if (readWriteSDBlockReq == `READ_SD_BLOCK)
      begin
        NextState_rwBlkSt <= `RD_CMD_SEND_CMD;
        next_spiCS_n <= 1'b0;
        next_readWriteSDBlockRdy <= 1'b0;
        next_readError <= `READ_NO_ERROR;
      end
      else if (readWriteSDBlockReq == `WRITE_SD_BLOCK)
      begin
        NextState_rwBlkSt <= `WR_CMD_SEND_CMD;
        next_spiCS_n <= 1'b0;
        next_readWriteSDBlockRdy <= 1'b0;
        next_writeError <= `WRITE_NO_ERROR;
      end
    end
    `WR_CMD_SEND_CMD:
    begin
      next_cmdByte <= 8'h58;
      //CMD24 Block Write
      next_dataByte1 <= blockAddr[31:24];
      next_dataByte2 <= blockAddr[23:16];
      next_dataByte3 <= blockAddr[15:8];
      next_dataByte4 <= blockAddr[7:0];
      next_checkSumByte <= 8'hff;
      next_sendCmdReq <= 1'b1;
      NextState_rwBlkSt <= `WR_CMD_DEL;
    end
    `WR_CMD_WT_FIN:
    begin
      if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00))
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_writeError <= `WRITE_CMD_ERROR;
      end
      else if (sendCmdRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `WR_TOKEN_FF1_ST;
      end
    end
    `WR_CMD_DEL:
    begin
      next_sendCmdReq <= 1'b0;
      NextState_rwBlkSt <= `WR_CMD_WT_FIN;
    end
    `WR_TOKEN_FF1_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `WR_TOKEN_FF2_ST;
    end
    `WR_TOKEN_FF1_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_TOKEN_FF1_FIN;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_TOKEN_FF2_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `WR_TOKEN_FE_ST;
    end
    `WR_TOKEN_FF2_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_TOKEN_FF2_FIN;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_TOKEN_FE_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `WR_DATA_LOOP_INIT;
    end
    `WR_TOKEN_FE_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_TOKEN_FE_FIN;
        next_txDataOut <= 8'hfe;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_BUSY_CHK_FIN:
    begin
      if (locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS)
      begin
        NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
        next_timeOutCnt <= timeOutCnt + 1'b1;
      end
      else if (timeOutCnt == `TWO_FIFTY_MS)
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_writeError <= `WRITE_BUSY_ERROR;
      end
      else
      begin
        NextState_rwBlkSt <= `WT_REQ;
      end
    end
    `WR_BUSY_WT_FIN1:
    begin
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `WR_BUSY_CHK_FIN;
        next_locRespByte <= rxDataIn;
      end
    end
    `WR_BUSY_DEL1:
    begin
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
      next_delCnt1 <= delCnt1 + 1'b1;
      next_delCnt2 <= 8'h00;
      if (delCnt1 == `MAX_8_BIT)
      begin
        NextState_rwBlkSt <= `WR_BUSY_WT_FIN1;
      end
      else
      begin
        NextState_rwBlkSt <= `WR_BUSY_DEL2;
      end
    end
    `WR_BUSY_SEND_CMD1:
    begin
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_rxDataRdyClr <= 1'b1;
      next_delCnt1 <= 8'h00;
      NextState_rwBlkSt <= `WR_BUSY_DEL1;
    end
    `WR_BUSY_DEL2:
    begin
      next_delCnt2 <= delCnt2 + 1'b1;
      if (delCnt2 == 8'hff)
      begin
        NextState_rwBlkSt <= `WR_BUSY_DEL1;
      end
    end
    `WR_BUSY_INIT_LOOP:
    begin
      next_timeOutCnt <= 12'h000;
      NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
    end
    `RD_CMD_SEND_CMD:
    begin
      next_cmdByte <= 8'h51;
      //CMD17 Block Read
      next_dataByte1 <= blockAddr[31:24];
      next_dataByte2 <= blockAddr[23:16];
      next_dataByte3 <= blockAddr[15:8];
      next_dataByte4 <= blockAddr[7:0];
      next_checkSumByte <= 8'hff;
      next_sendCmdReq <= 1'b1;
      NextState_rwBlkSt <= `RD_CMD_DEL;
    end
    `RD_CMD_WT_FIN:
    begin
      if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 || respByte != 8'h00))
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_readError <= `READ_CMD_ERROR;
      end
      else if (sendCmdRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_INIT_LOOP;
      end
    end
    `RD_CMD_DEL:
    begin
      next_sendCmdReq <= 1'b0;
      NextState_rwBlkSt <= `RD_CMD_WT_FIN;
    end
    `RD_TOKEN_CHK_LOOP:
    begin
      if (locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_DEL2;
        next_timeOutCnt <= timeOutCnt + 1'b1;
        next_delCnt1 <= 8'h00;
      end
      else if (timeOutCnt == `ONE_HUNDRED_MS)
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_readError <= `READ_TOKEN_ERROR;
      end
      else
      begin
        NextState_rwBlkSt <= `RD_DATA_CLR_RX;
        next_rxDataRdyClr <= 1'b1;
      end
    end
    `RD_TOKEN_WT_FIN:
    begin
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_CHK_LOOP;
        next_locRespByte <= rxDataIn;
      end
    end
    `RD_TOKEN_SEND_CMD:
    begin
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_rxDataRdyClr <= 1'b1;
      NextState_rwBlkSt <= `RD_TOKEN_DEL1;
    end
    `RD_TOKEN_DEL2:
    begin
      next_delCnt1 <= delCnt1 + 1'b1;
      next_delCnt2 <= 8'h00;
      if (delCnt1 == `MAX_8_BIT)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
      end
      else
      begin
        NextState_rwBlkSt <= `RD_TOKEN_DEL3;
      end
    end
    `RD_TOKEN_INIT_LOOP:
    begin
      next_timeOutCnt <= 12'h000;
      NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
    end
    `RD_TOKEN_DEL1:
    begin
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
      NextState_rwBlkSt <= `RD_TOKEN_WT_FIN;
    end
    `RD_TOKEN_DEL3:
    begin
      next_delCnt2 <= delCnt2 + 1'b1;
      if (delCnt2 == 8'hff)
      begin
        NextState_rwBlkSt <= `RD_TOKEN_DEL2;
      end
    end
    `RD_DATA_ST_LOOP:
    begin
      next_txDataWen <= 1'b1;
      next_txDataOut <= 8'hff;
      next_loopCnt <= loopCnt + 1'b1;
      NextState_rwBlkSt <= `RD_DATA_WT_DATA;
    end
    `RD_DATA_WT_DATA:
    begin
      next_txDataWen <= 1'b0;
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `RD_DATA_CHK_LOOP;
        next_rxFifoWen <= 1'b1;
        next_rxDataRdyClr <= 1'b1;
        next_rxFifoData <= rxDataIn;
      end
    end
    `RD_DATA_CHK_LOOP:
    begin
      if (loopCnt == 9'b000000000)
      begin
        NextState_rwBlkSt <= `RD_DATA_CS_ST1;
        next_rxDataRdyClr <= 1'b0;
        next_rxFifoWen <= 1'b0;
      end
      else
      begin
        NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
        next_rxDataRdyClr <= 1'b0;
        next_rxFifoWen <= 1'b0;
      end
    end
    `RD_DATA_CLR_RX:
    begin
      NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
      next_rxDataRdyClr <= 1'b0;
      next_loopCnt <= 9'b000000000;
    end
    `RD_DATA_CS_FIN2:
    begin
      next_txDataWen <= 1'b0;
      if (txDataEmpty == 1'b1)
      begin
        NextState_rwBlkSt <= `WT_REQ;
      end
    end
    `RD_DATA_CS_FIN1:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `RD_DATA_CS_ST2;
    end
    `RD_DATA_CS_ST1:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `RD_DATA_CS_FIN1;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `RD_DATA_CS_ST2:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `RD_DATA_CS_FIN2;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_D_FIN:
    begin
      next_txDataWen <= 1'b0;
      if (loopCnt == 9'b000000000)
      begin
        NextState_rwBlkSt <= `WR_DATA_CS_ST1;
      end
      else
      begin
        NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
      end
    end
    `WR_DATA_D_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_DATA_D_FIN;
        next_txDataOut <= txFifoData;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_RD_FIFO1:
    begin
      next_txFifoRen <= 1'b1;
      next_loopCnt <= loopCnt + 1'b1;
      NextState_rwBlkSt <= `WR_DATA_RD_FIFO2;
    end
    `WR_DATA_RD_FIFO2:
    begin
      next_txFifoRen <= 1'b0;
      NextState_rwBlkSt <= `WR_DATA_D_ST;
    end
    `WR_DATA_LOOP_INIT:
    begin
      next_loopCnt <= 9'b000000000;
      NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
    end
    `WR_DATA_CS_ST1:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_DATA_CS_FIN1;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_CS_FIN1:
    begin
      next_txDataWen <= 1'b0;
      NextState_rwBlkSt <= `WR_DATA_CS_ST2;
    end
    `WR_DATA_CS_FIN2:
    begin
      next_txDataWen <= 1'b0;
      next_timeOutCnt <= 12'h000;
      if (txDataEmpty == 1'b1)
      begin
        NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
      end
    end
    `WR_DATA_CS_ST2:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_rwBlkSt <= `WR_DATA_CS_FIN2;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `WR_DATA_CHK_RESP:
    begin
      if (timeOutCnt == `WR_RESP_TOUT)
      begin
        NextState_rwBlkSt <= `WT_REQ;
        next_writeError <= `WRITE_DATA_ERROR;
      end
      else if (locRespByte[4:0] == 5'h5)
      begin
        NextState_rwBlkSt <= `WR_BUSY_INIT_LOOP;
      end
      else
      begin
        NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
      end
    end
    `WR_DATA_REQ_RESP_ST:
    begin
      NextState_rwBlkSt <= `WR_DATA_DEL;
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_timeOutCnt <= timeOutCnt + 1'b1;
      next_rxDataRdyClr <= 1'b1;
    end
    `WR_DATA_REQ_RESP_FIN:
    begin
      if (rxDataRdy == 1'b1)
      begin
        NextState_rwBlkSt <= `WR_DATA_CHK_RESP;
        next_locRespByte <= rxDataIn;
      end
    end
    `WR_DATA_DEL:
    begin
      NextState_rwBlkSt <= `WR_DATA_REQ_RESP_FIN;
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst == 1'b1)
    CurrState_rwBlkSt <= `ST_RW_SD;
  else
    CurrState_rwBlkSt <= NextState_rwBlkSt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst == 1'b1)
  begin
    readWriteSDBlockRdy <= 1'b0;
    spiCS_n <= 1'b1;
    readError <= 1'b0;
    writeError <= 1'b0;
    txDataOut <= 8'h00;
    txDataWen <= 1'b0;
    rxDataRdyClr <= 1'b0;
    cmdByte <= 8'h00;
    dataByte1 <= 8'h00;
    dataByte2 <= 8'h00;
    dataByte3 <= 8'h00;
    dataByte4 <= 8'h00;
    checkSumByte <= 8'h00;
    sendCmdReq <= 1'b0;
    txFifoRen <= 1'b0;
    rxFifoWen <= 1'b0;
    rxFifoData <= 8'h00;
    loopCnt <= 8'h00;
    delCnt1 <= 8'h00;
    delCnt2 <= 8'h00;
    timeOutCnt <= 12'h000;
    locRespByte <= 8'h00;
  end
  else
  begin
    readWriteSDBlockRdy <= next_readWriteSDBlockRdy;
    spiCS_n <= next_spiCS_n;
    readError <= next_readError;
    writeError <= next_writeError;
    txDataOut <= next_txDataOut;
    txDataWen <= next_txDataWen;
    rxDataRdyClr <= next_rxDataRdyClr;
    cmdByte <= next_cmdByte;
    dataByte1 <= next_dataByte1;
    dataByte2 <= next_dataByte2;
    dataByte3 <= next_dataByte3;
    dataByte4 <= next_dataByte4;
    checkSumByte <= next_checkSumByte;
    sendCmdReq <= next_sendCmdReq;
    txFifoRen <= next_txFifoRen;
    rxFifoWen <= next_rxFifoWen;
    rxFifoData <= next_rxFifoData;
    loopCnt <= next_loopCnt;
    delCnt1 <= next_delCnt1;
    delCnt2 <= next_delCnt2;
    timeOutCnt <= next_timeOutCnt;
    locRespByte <= next_locRespByte;
  end
end
 
endmodule

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[/] [spimaster/] [trunk/] [RTL/] [readWriteSDBlock.v] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// readWriteSDBlock.v ////`
5			`//// ////`
6			`//// This file is part of the spiMaster opencores effort.`
7			`//// <http://www.opencores.org/cores//> ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`//// If readWriteSDBlockReq equals WRITE_SD_BLOCK or`
11			`//// READ_SD_BLOCK, then write or read a 512 byte block`
12			`//// of SD memory`
13			`////`
14			`//// ////`
15			`//// To Do: ////`
16			`////`
17			`//// ////`
18			`//// Author(s): ////`
19			`//// - Steve Fielding, sfielding@base2designs.com ////`
20			`//// ////`
21			`//////////////////////////////////////////////////////////////////////`
22			`//// ////`
23			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
24			`//// ////`
25			`//// This source file may be used and distributed without ////`
26			`//// restriction provided that this copyright statement is not ////`
27			`//// removed from the file and that any derivative work contains ////`
28			`//// the original copyright notice and the associated disclaimer. ////`
29			`//// ////`
30			`//// This source file is free software; you can redistribute it ////`
31			`//// and/or modify it under the terms of the GNU Lesser General ////`
32			`//// Public License as published by the Free Software Foundation; ////`
33			`//// either version 2.1 of the License, or (at your option) any ////`
34			`//// later version. ////`
35			`//// ////`
36			`//// This source is distributed in the hope that it will be ////`
37			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
38			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
39			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
40			`//// details. ////`
41			`//// ////`
42			`//// You should have received a copy of the GNU Lesser General ////`
43			`//// Public License along with this source; if not, download it ////`
44			`//// from <http://www.opencores.org/lgpl.shtml> ////`
45			`//// ////`
46			`//////////////////////////////////////////////////////////////////////`
47			`//`
48			`include "timescale.v"
49			`include "spiMaster_defines.v"
50
51			`module readWriteSDBlock (blockAddr, checkSumByte, clk, cmdByte, dataByte1, dataByte2, dataByte3, dataByte4, readError, readWriteSDBlockRdy, readWriteSDBlockReq, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, rxFifoData, rxFifoWen, sendCmdRdy, sendCmdReq, spiCS_n, txDataEmpty, txDataFull, txDataOut, txDataWen, txFifoData, txFifoRen, writeError);`
52			`input [31:0]blockAddr;`
53			`input clk;`
54			`input [1:0]readWriteSDBlockReq;`
55			`input [7:0]respByte;`
56			`input respTout;`
57			`input rst;`
58			`input [7:0]rxDataIn;`
59			`input rxDataRdy;`
60			`input sendCmdRdy;`
61			`input txDataEmpty;`
62			`input txDataFull;`
63			`input [7:0]txFifoData;`
64			`output [7:0]checkSumByte;`
65			`output [7:0]cmdByte;`
66			`output [7:0]dataByte1;`
67			`output [7:0]dataByte2;`
68			`output [7:0]dataByte3;`
69			`output [7:0]dataByte4;`
70			`output [1:0]readError;`
71			`output readWriteSDBlockRdy;`
72			`output rxDataRdyClr;`
73			`output [7:0]rxFifoData;`
74			`output rxFifoWen;`
75			`output sendCmdReq;`
76			`output spiCS_n;`
77			`output [7:0]txDataOut;`
78			`output txDataWen;`
79			`output txFifoRen;`
80			`output [1:0]writeError;`
81
82			`wire [31:0]blockAddr;`
83			`reg [7:0]checkSumByte, next_checkSumByte;`
84			`wire clk;`
85			`reg [7:0]cmdByte, next_cmdByte;`
86			`reg [7:0]dataByte1, next_dataByte1;`
87			`reg [7:0]dataByte2, next_dataByte2;`
88			`reg [7:0]dataByte3, next_dataByte3;`
89			`reg [7:0]dataByte4, next_dataByte4;`
90			`reg [1:0]readError, next_readError;`
91			`reg readWriteSDBlockRdy, next_readWriteSDBlockRdy;`
92			`wire [1:0]readWriteSDBlockReq;`
93			`wire [7:0]respByte;`
94			`wire respTout;`
95			`wire rst;`
96			`wire [7:0]rxDataIn;`
97			`wire rxDataRdy;`
98			`reg rxDataRdyClr, next_rxDataRdyClr;`
99			`reg [7:0]rxFifoData, next_rxFifoData;`
100			`reg rxFifoWen, next_rxFifoWen;`
101			`wire sendCmdRdy;`
102			`reg sendCmdReq, next_sendCmdReq;`
103			`reg spiCS_n, next_spiCS_n;`
104			`wire txDataEmpty;`
105			`wire txDataFull;`
106			`reg [7:0]txDataOut, next_txDataOut;`
107			`reg txDataWen, next_txDataWen;`
108			`wire [7:0]txFifoData;`
109			`reg txFifoRen, next_txFifoRen;`
110			`reg [1:0]writeError, next_writeError;`
111
112			`// diagram signals declarations`
113			`reg [7:0]delCnt1, next_delCnt1;`
114			`reg [7:0]delCnt2, next_delCnt2;`
115			`reg [7:0]locRespByte, next_locRespByte;`
116			`reg [8:0]loopCnt, next_loopCnt;`
117			`reg [11:0]timeOutCnt, next_timeOutCnt;`
118
119			`// BINARY ENCODED state machine: rwBlkSt`
120			`// State codes definitions:`
121			`define ST_RW_SD 6'b000000
122			`define WR_CMD_SEND_CMD 6'b000001
123			`define WR_CMD_WT_FIN 6'b000010
124			`define WR_CMD_DEL 6'b000011
125			`define WT_REQ 6'b000100
126			`define WR_TOKEN_FF1_FIN 6'b000101
127			`define WR_TOKEN_FF1_ST 6'b000110
128			`define WR_TOKEN_FF2_FIN 6'b000111
129			`define WR_TOKEN_FF2_ST 6'b001000
130			`define WR_TOKEN_FE_FIN 6'b001001
131			`define WR_TOKEN_FE_ST 6'b001010
132			`define WR_DATA_D_FIN 6'b001011
133			`define WR_DATA_D_ST 6'b001100
134			`define WR_DATA_RD_FIFO1 6'b001101
135			`define WR_DATA_RD_FIFO2 6'b001110
136			`define WR_DATA_LOOP_INIT 6'b001111
137			`define WR_DATA_CS_ST1 6'b010000
138			`define WR_DATA_CS_FIN1 6'b010001
139			`define WR_DATA_CS_FIN2 6'b010010
140			`define WR_DATA_CS_ST2 6'b010011
141			`define WR_DATA_CHK_RESP 6'b010100
142			`define WR_DATA_REQ_RESP_ST 6'b010101
143			`define WR_DATA_REQ_RESP_FIN 6'b010110
144			`define RD_CMD_SEND_CMD 6'b010111
145			`define RD_CMD_WT_FIN 6'b011000
146			`define RD_CMD_DEL 6'b011001
147			`define RD_TOKEN_CHK_LOOP 6'b011010
148			`define RD_TOKEN_WT_FIN 6'b011011
149			`define RD_TOKEN_SEND_CMD 6'b011100
150			`define RD_TOKEN_DEL2 6'b011101
151			`define RD_TOKEN_INIT_LOOP 6'b011110
152			`define RD_TOKEN_DEL1 6'b011111
153			`define RD_DATA_ST_LOOP 6'b100000
154			`define RD_DATA_WT_DATA 6'b100001
155			`define RD_DATA_CHK_LOOP 6'b100010
156			`define RD_DATA_CLR_RX 6'b100011
157			`define RD_DATA_CS_FIN2 6'b100100
158			`define RD_DATA_CS_FIN1 6'b100101
159			`define RD_DATA_CS_ST1 6'b100110
160			`define RD_DATA_CS_ST2 6'b100111
161			`define WR_BUSY_CHK_FIN 6'b101000
162			`define WR_BUSY_WT_FIN1 6'b101001
163			`define WR_BUSY_DEL1 6'b101010
164			`define WR_BUSY_SEND_CMD1 6'b101011
165			`define WR_BUSY_DEL2 6'b101100
166			`define WR_BUSY_INIT_LOOP 6'b101101
167			`define RD_TOKEN_DEL3 6'b101110
168			`define WR_DATA_DEL 6'b101111
169
170			`reg [5:0]CurrState_rwBlkSt, NextState_rwBlkSt;`
171
172			`// Diagram actions (continuous assignments allowed only: assign ...)`
173			`// diagram ACTION`
174
175
176			`// Machine: rwBlkSt`
177
178			`// NextState logic (combinatorial)`
179			`always @ (blockAddr or sendCmdRdy or respTout or respByte or readWriteSDBlockReq or txDataFull or loopCnt or txFifoData or txDataEmpty or timeOutCnt or locRespByte or rxDataRdy or rxDataIn or delCnt1 or delCnt2 or readWriteSDBlockRdy or spiCS_n or readError or writeError or txDataOut or txDataWen or rxDataRdyClr or cmdByte or dataByte1 or dataByte2 or dataByte3 or dataByte4 or checkSumByte or sendCmdReq or txFifoRen or rxFifoWen or rxFifoData or CurrState_rwBlkSt)`
180			`begin`
181			`NextState_rwBlkSt <= CurrState_rwBlkSt;`
182			`// Set default values for outputs and signals`
183			`next_readWriteSDBlockRdy <= readWriteSDBlockRdy;`
184			`next_spiCS_n <= spiCS_n;`
185			`next_readError <= readError;`
186			`next_writeError <= writeError;`
187			`next_txDataOut <= txDataOut;`
188			`next_txDataWen <= txDataWen;`
189			`next_rxDataRdyClr <= rxDataRdyClr;`
190			`next_cmdByte <= cmdByte;`
191			`next_dataByte1 <= dataByte1;`
192			`next_dataByte2 <= dataByte2;`
193			`next_dataByte3 <= dataByte3;`
194			`next_dataByte4 <= dataByte4;`
195			`next_checkSumByte <= checkSumByte;`
196			`next_sendCmdReq <= sendCmdReq;`
197			`next_loopCnt <= loopCnt;`
198			`next_delCnt1 <= delCnt1;`
199			`next_delCnt2 <= delCnt2;`
200			`next_txFifoRen <= txFifoRen;`
201			`next_rxFifoWen <= rxFifoWen;`
202			`next_rxFifoData <= rxFifoData;`
203			`next_timeOutCnt <= timeOutCnt;`
204			`next_locRespByte <= locRespByte;`
205			`case (CurrState_rwBlkSt) // synopsys parallel_case full_case`
206			`ST_RW_SD:
207			`begin`
208			`next_readWriteSDBlockRdy <= 1'b0;`
209			`next_spiCS_n <= 1'b1;`
210			`next_readError <= 1'b0;`
211			`next_writeError <= 1'b0;`
212			`next_txDataOut <= 8'h00;`
213			`next_txDataWen <= 1'b0;`
214			`next_rxDataRdyClr <= 1'b0;`
215			`next_cmdByte <= 8'h00;`
216			`next_dataByte1 <= 8'h00;`
217			`next_dataByte2 <= 8'h00;`
218			`next_dataByte3 <= 8'h00;`
219			`next_dataByte4 <= 8'h00;`
220			`next_checkSumByte <= 8'h00;`
221			`next_sendCmdReq <= 1'b0;`
222			`next_loopCnt <= 8'h00;`
223			`next_delCnt1 <= 8'h00;`
224			`next_delCnt2 <= 8'h00;`
225			next_readError <= `READ_NO_ERROR;
226			next_writeError <= `WRITE_NO_ERROR;
227			`next_txFifoRen <= 1'b0;`
228			`next_rxFifoWen <= 1'b0;`
229			`next_rxFifoData <= 8'h00;`
230			`next_timeOutCnt <= 12'h000;`
231			`next_locRespByte <= 8'h00;`
232			NextState_rwBlkSt <= `WT_REQ;
233			`end`
234			`WT_REQ:
235			`begin`
236			`next_spiCS_n <= 1'b1;`
237			`next_readWriteSDBlockRdy <= 1'b1;`
238			`next_cmdByte <= 8'h00;`
239			`next_dataByte1 <= 8'h00;`
240			`next_dataByte2 <= 8'h00;`
241			`next_dataByte3 <= 8'h00;`
242			`next_dataByte4 <= 8'h00;`
243			`next_checkSumByte <= 8'h00;`
244			if (readWriteSDBlockReq == `READ_SD_BLOCK)
245			`begin`
246			NextState_rwBlkSt <= `RD_CMD_SEND_CMD;
247			`next_spiCS_n <= 1'b0;`
248			`next_readWriteSDBlockRdy <= 1'b0;`
249			next_readError <= `READ_NO_ERROR;
250			`end`
251			else if (readWriteSDBlockReq == `WRITE_SD_BLOCK)
252			`begin`
253			NextState_rwBlkSt <= `WR_CMD_SEND_CMD;
254			`next_spiCS_n <= 1'b0;`
255			`next_readWriteSDBlockRdy <= 1'b0;`
256			next_writeError <= `WRITE_NO_ERROR;
257			`end`
258			`end`
259			`WR_CMD_SEND_CMD:
260			`begin`
261			`next_cmdByte <= 8'h58;`
262			`//CMD24 Block Write`
263			`next_dataByte1 <= blockAddr[31:24];`
264			`next_dataByte2 <= blockAddr[23:16];`
265			`next_dataByte3 <= blockAddr[15:8];`
266			`next_dataByte4 <= blockAddr[7:0];`
267			`next_checkSumByte <= 8'hff;`
268			`next_sendCmdReq <= 1'b1;`
269			NextState_rwBlkSt <= `WR_CMD_DEL;
270			`end`
271			`WR_CMD_WT_FIN:
272			`begin`
273			`if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 \|\| respByte != 8'h00))`
274			`begin`
275			NextState_rwBlkSt <= `WT_REQ;
276			next_writeError <= `WRITE_CMD_ERROR;
277			`end`
278			`else if (sendCmdRdy == 1'b1)`
279			`begin`
280			NextState_rwBlkSt <= `WR_TOKEN_FF1_ST;
281			`end`
282			`end`
283			`WR_CMD_DEL:
284			`begin`
285			`next_sendCmdReq <= 1'b0;`
286			NextState_rwBlkSt <= `WR_CMD_WT_FIN;
287			`end`
288			`WR_TOKEN_FF1_FIN:
289			`begin`
290			`next_txDataWen <= 1'b0;`
291			NextState_rwBlkSt <= `WR_TOKEN_FF2_ST;
292			`end`
293			`WR_TOKEN_FF1_ST:
294			`begin`
295			`if (txDataFull == 1'b0)`
296			`begin`
297			NextState_rwBlkSt <= `WR_TOKEN_FF1_FIN;
298			`next_txDataOut <= 8'hff;`
299			`next_txDataWen <= 1'b1;`
300			`end`
301			`end`
302			`WR_TOKEN_FF2_FIN:
303			`begin`
304			`next_txDataWen <= 1'b0;`
305			NextState_rwBlkSt <= `WR_TOKEN_FE_ST;
306			`end`
307			`WR_TOKEN_FF2_ST:
308			`begin`
309			`if (txDataFull == 1'b0)`
310			`begin`
311			NextState_rwBlkSt <= `WR_TOKEN_FF2_FIN;
312			`next_txDataOut <= 8'hff;`
313			`next_txDataWen <= 1'b1;`
314			`end`
315			`end`
316			`WR_TOKEN_FE_FIN:
317			`begin`
318			`next_txDataWen <= 1'b0;`
319			NextState_rwBlkSt <= `WR_DATA_LOOP_INIT;
320			`end`
321			`WR_TOKEN_FE_ST:
322			`begin`
323			`if (txDataFull == 1'b0)`
324			`begin`
325			NextState_rwBlkSt <= `WR_TOKEN_FE_FIN;
326			`next_txDataOut <= 8'hfe;`
327			`next_txDataWen <= 1'b1;`
328			`end`
329			`end`
330			`WR_BUSY_CHK_FIN:
331			`begin`
332			if (locRespByte == 8'h00 && timeOutCnt != `TWO_FIFTY_MS)
333			`begin`
334			NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
335			`next_timeOutCnt <= timeOutCnt + 1'b1;`
336			`end`
337			else if (timeOutCnt == `TWO_FIFTY_MS)
338			`begin`
339			NextState_rwBlkSt <= `WT_REQ;
340			next_writeError <= `WRITE_BUSY_ERROR;
341			`end`
342			`else`
343			`begin`
344			NextState_rwBlkSt <= `WT_REQ;
345			`end`
346			`end`
347			`WR_BUSY_WT_FIN1:
348			`begin`
349			`if (rxDataRdy == 1'b1)`
350			`begin`
351			NextState_rwBlkSt <= `WR_BUSY_CHK_FIN;
352			`next_locRespByte <= rxDataIn;`
353			`end`
354			`end`
355			`WR_BUSY_DEL1:
356			`begin`
357			`next_txDataWen <= 1'b0;`
358			`next_rxDataRdyClr <= 1'b0;`
359			`next_delCnt1 <= delCnt1 + 1'b1;`
360			`next_delCnt2 <= 8'h00;`
361			if (delCnt1 == `MAX_8_BIT)
362			`begin`
363			NextState_rwBlkSt <= `WR_BUSY_WT_FIN1;
364			`end`
365			`else`
366			`begin`
367			NextState_rwBlkSt <= `WR_BUSY_DEL2;
368			`end`
369			`end`
370			`WR_BUSY_SEND_CMD1:
371			`begin`
372			`next_txDataOut <= 8'hff;`
373			`next_txDataWen <= 1'b1;`
374			`next_rxDataRdyClr <= 1'b1;`
375			`next_delCnt1 <= 8'h00;`
376			NextState_rwBlkSt <= `WR_BUSY_DEL1;
377			`end`
378			`WR_BUSY_DEL2:
379			`begin`
380			`next_delCnt2 <= delCnt2 + 1'b1;`
381			`if (delCnt2 == 8'hff)`
382			`begin`
383			NextState_rwBlkSt <= `WR_BUSY_DEL1;
384			`end`
385			`end`
386			`WR_BUSY_INIT_LOOP:
387			`begin`
388			`next_timeOutCnt <= 12'h000;`
389			NextState_rwBlkSt <= `WR_BUSY_SEND_CMD1;
390			`end`
391			`RD_CMD_SEND_CMD:
392			`begin`
393			`next_cmdByte <= 8'h51;`
394			`//CMD17 Block Read`
395			`next_dataByte1 <= blockAddr[31:24];`
396			`next_dataByte2 <= blockAddr[23:16];`
397			`next_dataByte3 <= blockAddr[15:8];`
398			`next_dataByte4 <= blockAddr[7:0];`
399			`next_checkSumByte <= 8'hff;`
400			`next_sendCmdReq <= 1'b1;`
401			NextState_rwBlkSt <= `RD_CMD_DEL;
402			`end`
403			`RD_CMD_WT_FIN:
404			`begin`
405			`if ((sendCmdRdy == 1'b1) && (respTout == 1'b1 \|\| respByte != 8'h00))`
406			`begin`
407			NextState_rwBlkSt <= `WT_REQ;
408			next_readError <= `READ_CMD_ERROR;
409			`end`
410			`else if (sendCmdRdy == 1'b1)`
411			`begin`
412			NextState_rwBlkSt <= `RD_TOKEN_INIT_LOOP;
413			`end`
414			`end`
415			`RD_CMD_DEL:
416			`begin`
417			`next_sendCmdReq <= 1'b0;`
418			NextState_rwBlkSt <= `RD_CMD_WT_FIN;
419			`end`
420			`RD_TOKEN_CHK_LOOP:
421			`begin`
422			if (locRespByte != 8'hfe && timeOutCnt != `ONE_HUNDRED_MS)
423			`begin`
424			NextState_rwBlkSt <= `RD_TOKEN_DEL2;
425			`next_timeOutCnt <= timeOutCnt + 1'b1;`
426			`next_delCnt1 <= 8'h00;`
427			`end`
428			else if (timeOutCnt == `ONE_HUNDRED_MS)
429			`begin`
430			NextState_rwBlkSt <= `WT_REQ;
431			next_readError <= `READ_TOKEN_ERROR;
432			`end`
433			`else`
434			`begin`
435			NextState_rwBlkSt <= `RD_DATA_CLR_RX;
436			`next_rxDataRdyClr <= 1'b1;`
437			`end`
438			`end`
439			`RD_TOKEN_WT_FIN:
440			`begin`
441			`if (rxDataRdy == 1'b1)`
442			`begin`
443			NextState_rwBlkSt <= `RD_TOKEN_CHK_LOOP;
444			`next_locRespByte <= rxDataIn;`
445			`end`
446			`end`
447			`RD_TOKEN_SEND_CMD:
448			`begin`
449			`next_txDataOut <= 8'hff;`
450			`next_txDataWen <= 1'b1;`
451			`next_rxDataRdyClr <= 1'b1;`
452			NextState_rwBlkSt <= `RD_TOKEN_DEL1;
453			`end`
454			`RD_TOKEN_DEL2:
455			`begin`
456			`next_delCnt1 <= delCnt1 + 1'b1;`
457			`next_delCnt2 <= 8'h00;`
458			if (delCnt1 == `MAX_8_BIT)
459			`begin`
460			NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
461			`end`
462			`else`
463			`begin`
464			NextState_rwBlkSt <= `RD_TOKEN_DEL3;
465			`end`
466			`end`
467			`RD_TOKEN_INIT_LOOP:
468			`begin`
469			`next_timeOutCnt <= 12'h000;`
470			NextState_rwBlkSt <= `RD_TOKEN_SEND_CMD;
471			`end`
472			`RD_TOKEN_DEL1:
473			`begin`
474			`next_txDataWen <= 1'b0;`
475			`next_rxDataRdyClr <= 1'b0;`
476			NextState_rwBlkSt <= `RD_TOKEN_WT_FIN;
477			`end`
478			`RD_TOKEN_DEL3:
479			`begin`
480			`next_delCnt2 <= delCnt2 + 1'b1;`
481			`if (delCnt2 == 8'hff)`
482			`begin`
483			NextState_rwBlkSt <= `RD_TOKEN_DEL2;
484			`end`
485			`end`
486			`RD_DATA_ST_LOOP:
487			`begin`
488			`next_txDataWen <= 1'b1;`
489			`next_txDataOut <= 8'hff;`
490			`next_loopCnt <= loopCnt + 1'b1;`
491			NextState_rwBlkSt <= `RD_DATA_WT_DATA;
492			`end`
493			`RD_DATA_WT_DATA:
494			`begin`
495			`next_txDataWen <= 1'b0;`
496			`if (rxDataRdy == 1'b1)`
497			`begin`
498			NextState_rwBlkSt <= `RD_DATA_CHK_LOOP;
499			`next_rxFifoWen <= 1'b1;`
500			`next_rxDataRdyClr <= 1'b1;`
501			`next_rxFifoData <= rxDataIn;`
502			`end`
503			`end`
504			`RD_DATA_CHK_LOOP:
505			`begin`
506			`if (loopCnt == 9'b000000000)`
507			`begin`
508			NextState_rwBlkSt <= `RD_DATA_CS_ST1;
509			`next_rxDataRdyClr <= 1'b0;`
510			`next_rxFifoWen <= 1'b0;`
511			`end`
512			`else`
513			`begin`
514			NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
515			`next_rxDataRdyClr <= 1'b0;`
516			`next_rxFifoWen <= 1'b0;`
517			`end`
518			`end`
519			`RD_DATA_CLR_RX:
520			`begin`
521			NextState_rwBlkSt <= `RD_DATA_ST_LOOP;
522			`next_rxDataRdyClr <= 1'b0;`
523			`next_loopCnt <= 9'b000000000;`
524			`end`
525			`RD_DATA_CS_FIN2:
526			`begin`
527			`next_txDataWen <= 1'b0;`
528			`if (txDataEmpty == 1'b1)`
529			`begin`
530			NextState_rwBlkSt <= `WT_REQ;
531			`end`
532			`end`
533			`RD_DATA_CS_FIN1:
534			`begin`
535			`next_txDataWen <= 1'b0;`
536			NextState_rwBlkSt <= `RD_DATA_CS_ST2;
537			`end`
538			`RD_DATA_CS_ST1:
539			`begin`
540			`if (txDataFull == 1'b0)`
541			`begin`
542			NextState_rwBlkSt <= `RD_DATA_CS_FIN1;
543			`next_txDataOut <= 8'hff;`
544			`next_txDataWen <= 1'b1;`
545			`end`
546			`end`
547			`RD_DATA_CS_ST2:
548			`begin`
549			`if (txDataFull == 1'b0)`
550			`begin`
551			NextState_rwBlkSt <= `RD_DATA_CS_FIN2;
552			`next_txDataOut <= 8'hff;`
553			`next_txDataWen <= 1'b1;`
554			`end`
555			`end`
556			`WR_DATA_D_FIN:
557			`begin`
558			`next_txDataWen <= 1'b0;`
559			`if (loopCnt == 9'b000000000)`
560			`begin`
561			NextState_rwBlkSt <= `WR_DATA_CS_ST1;
562			`end`
563			`else`
564			`begin`
565			NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
566			`end`
567			`end`
568			`WR_DATA_D_ST:
569			`begin`
570			`if (txDataFull == 1'b0)`
571			`begin`
572			NextState_rwBlkSt <= `WR_DATA_D_FIN;
573			`next_txDataOut <= txFifoData;`
574			`next_txDataWen <= 1'b1;`
575			`end`
576			`end`
577			`WR_DATA_RD_FIFO1:
578			`begin`
579			`next_txFifoRen <= 1'b1;`
580			`next_loopCnt <= loopCnt + 1'b1;`
581			NextState_rwBlkSt <= `WR_DATA_RD_FIFO2;
582			`end`
583			`WR_DATA_RD_FIFO2:
584			`begin`
585			`next_txFifoRen <= 1'b0;`
586			NextState_rwBlkSt <= `WR_DATA_D_ST;
587			`end`
588			`WR_DATA_LOOP_INIT:
589			`begin`
590			`next_loopCnt <= 9'b000000000;`
591			NextState_rwBlkSt <= `WR_DATA_RD_FIFO1;
592			`end`
593			`WR_DATA_CS_ST1:
594			`begin`
595			`if (txDataFull == 1'b0)`
596			`begin`
597			NextState_rwBlkSt <= `WR_DATA_CS_FIN1;
598			`next_txDataOut <= 8'hff;`
599			`next_txDataWen <= 1'b1;`
600			`end`
601			`end`
602			`WR_DATA_CS_FIN1:
603			`begin`
604			`next_txDataWen <= 1'b0;`
605			NextState_rwBlkSt <= `WR_DATA_CS_ST2;
606			`end`
607			`WR_DATA_CS_FIN2:
608			`begin`
609			`next_txDataWen <= 1'b0;`
610			`next_timeOutCnt <= 12'h000;`
611			`if (txDataEmpty == 1'b1)`
612			`begin`
613			NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
614			`end`
615			`end`
616			`WR_DATA_CS_ST2:
617			`begin`
618			`if (txDataFull == 1'b0)`
619			`begin`
620			NextState_rwBlkSt <= `WR_DATA_CS_FIN2;
621			`next_txDataOut <= 8'hff;`
622			`next_txDataWen <= 1'b1;`
623			`end`
624			`end`
625			`WR_DATA_CHK_RESP:
626			`begin`
627			if (timeOutCnt == `WR_RESP_TOUT)
628			`begin`
629			NextState_rwBlkSt <= `WT_REQ;
630			next_writeError <= `WRITE_DATA_ERROR;
631			`end`
632			`else if (locRespByte[4:0] == 5'h5)`
633			`begin`
634			NextState_rwBlkSt <= `WR_BUSY_INIT_LOOP;
635			`end`
636			`else`
637			`begin`
638			NextState_rwBlkSt <= `WR_DATA_REQ_RESP_ST;
639			`end`
640			`end`
641			`WR_DATA_REQ_RESP_ST:
642			`begin`
643			NextState_rwBlkSt <= `WR_DATA_DEL;
644			`next_txDataOut <= 8'hff;`
645			`next_txDataWen <= 1'b1;`
646			`next_timeOutCnt <= timeOutCnt + 1'b1;`
647			`next_rxDataRdyClr <= 1'b1;`
648			`end`
649			`WR_DATA_REQ_RESP_FIN:
650			`begin`
651			`if (rxDataRdy == 1'b1)`
652			`begin`
653			NextState_rwBlkSt <= `WR_DATA_CHK_RESP;
654			`next_locRespByte <= rxDataIn;`
655			`end`
656			`end`
657			`WR_DATA_DEL:
658			`begin`
659			NextState_rwBlkSt <= `WR_DATA_REQ_RESP_FIN;
660			`next_txDataWen <= 1'b0;`
661			`next_rxDataRdyClr <= 1'b0;`
662			`end`
663			`endcase`
664			`end`
665
666			`// Current State Logic (sequential)`
667			`always @ (posedge clk)`
668			`begin`
669			`if (rst == 1'b1)`
670			CurrState_rwBlkSt <= `ST_RW_SD;
671			`else`
672			`CurrState_rwBlkSt <= NextState_rwBlkSt;`
673			`end`
674
675			`// Registered outputs logic`
676			`always @ (posedge clk)`
677			`begin`
678			`if (rst == 1'b1)`
679			`begin`
680			`readWriteSDBlockRdy <= 1'b0;`
681			`spiCS_n <= 1'b1;`
682			`readError <= 1'b0;`
683			`writeError <= 1'b0;`
684			`txDataOut <= 8'h00;`
685			`txDataWen <= 1'b0;`
686			`rxDataRdyClr <= 1'b0;`
687			`cmdByte <= 8'h00;`
688			`dataByte1 <= 8'h00;`
689			`dataByte2 <= 8'h00;`
690			`dataByte3 <= 8'h00;`
691			`dataByte4 <= 8'h00;`
692			`checkSumByte <= 8'h00;`
693			`sendCmdReq <= 1'b0;`
694			`txFifoRen <= 1'b0;`
695			`rxFifoWen <= 1'b0;`
696			`rxFifoData <= 8'h00;`
697			`loopCnt <= 8'h00;`
698			`delCnt1 <= 8'h00;`
699			`delCnt2 <= 8'h00;`
700			`timeOutCnt <= 12'h000;`
701			`locRespByte <= 8'h00;`
702			`end`
703			`else`
704			`begin`
705			`readWriteSDBlockRdy <= next_readWriteSDBlockRdy;`
706			`spiCS_n <= next_spiCS_n;`
707			`readError <= next_readError;`
708			`writeError <= next_writeError;`
709			`txDataOut <= next_txDataOut;`
710			`txDataWen <= next_txDataWen;`
711			`rxDataRdyClr <= next_rxDataRdyClr;`
712			`cmdByte <= next_cmdByte;`
713			`dataByte1 <= next_dataByte1;`
714			`dataByte2 <= next_dataByte2;`
715			`dataByte3 <= next_dataByte3;`
716			`dataByte4 <= next_dataByte4;`
717			`checkSumByte <= next_checkSumByte;`
718			`sendCmdReq <= next_sendCmdReq;`
719			`txFifoRen <= next_txFifoRen;`
720			`rxFifoWen <= next_rxFifoWen;`
721			`rxFifoData <= next_rxFifoData;`
722			`loopCnt <= next_loopCnt;`
723			`delCnt1 <= next_delCnt1;`
724			`delCnt2 <= next_delCnt2;`
725			`timeOutCnt <= next_timeOutCnt;`
726			`locRespByte <= next_locRespByte;`
727			`end`
728			`end`
729
730			`endmodule`