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sfielding |
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// readWriteSPIWireData.v ////
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//// ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Wait for TX data bytes. When data is ready generate
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//// SPI TX data, SPI CLK, and read SPI RX data
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "spiMaster_defines.v"
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module readWriteSPIWireData (clk, clkDelay, rst, rxDataOut, rxDataRdySet, spiClkOut, spiDataIn, spiDataOut, txDataEmpty, txDataFull, txDataFullClr, txDataIn);
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input clk;
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input [7:0]clkDelay;
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input rst;
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input spiDataIn;
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input txDataFull;
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input [7:0]txDataIn;
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output [7:0]rxDataOut;
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output rxDataRdySet;
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output spiClkOut;
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output spiDataOut;
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output txDataEmpty;
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output txDataFullClr;
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wire clk;
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wire [7:0]clkDelay;
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wire rst;
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reg [7:0]rxDataOut, next_rxDataOut;
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reg rxDataRdySet, next_rxDataRdySet;
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reg spiClkOut, next_spiClkOut;
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wire spiDataIn;
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reg spiDataOut, next_spiDataOut;
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reg txDataEmpty, next_txDataEmpty;
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wire txDataFull;
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reg txDataFullClr, next_txDataFullClr;
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wire [7:0]txDataIn;
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// diagram signals declarations
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reg [3:0]bitCnt, next_bitCnt;
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reg [7:0]clkDelayCnt, next_clkDelayCnt;
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reg [7:0]rxDataShiftReg, next_rxDataShiftReg;
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reg [7:0]txDataShiftReg, next_txDataShiftReg;
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// BINARY ENCODED state machine: rwSPISt
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// State codes definitions:
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`define WT_TX_DATA 2'b00
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`define CLK_HI 2'b01
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`define CLK_LO 2'b10
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`define ST_RW_WIRE 2'b11
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reg [1:0]CurrState_rwSPISt, NextState_rwSPISt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// diagram ACTION
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// Machine: rwSPISt
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// NextState logic (combinatorial)
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always @ (txDataFull or txDataIn or clkDelayCnt or clkDelay or txDataShiftReg or rxDataShiftReg or spiDataIn or bitCnt or rxDataRdySet or txDataEmpty or txDataFullClr or spiClkOut or spiDataOut or rxDataOut or CurrState_rwSPISt)
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sfielding |
begin
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NextState_rwSPISt <= CurrState_rwSPISt;
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// Set default values for outputs and signals
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next_rxDataRdySet <= rxDataRdySet;
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next_txDataEmpty <= txDataEmpty;
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next_txDataShiftReg <= txDataShiftReg;
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next_rxDataShiftReg <= rxDataShiftReg;
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next_bitCnt <= bitCnt;
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next_clkDelayCnt <= clkDelayCnt;
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next_txDataFullClr <= txDataFullClr;
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next_spiClkOut <= spiClkOut;
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next_spiDataOut <= spiDataOut;
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next_rxDataOut <= rxDataOut;
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case (CurrState_rwSPISt) // synopsys parallel_case full_case
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`WT_TX_DATA:
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begin
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next_rxDataRdySet <= 1'b0;
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next_txDataEmpty <= 1'b1;
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if (txDataFull == 1'b1)
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begin
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NextState_rwSPISt <= `CLK_HI;
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next_txDataShiftReg <= txDataIn;
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next_rxDataShiftReg <= 8'h00;
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next_bitCnt <= 4'h0;
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next_clkDelayCnt <= 8'h00;
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next_txDataFullClr <= 1'b1;
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next_txDataEmpty <= 1'b0;
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end
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end
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`CLK_HI:
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begin
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next_clkDelayCnt <= clkDelayCnt + 1'b1;
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next_txDataFullClr <= 1'b0;
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next_rxDataRdySet <= 1'b0;
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if (clkDelayCnt == clkDelay)
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begin
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NextState_rwSPISt <= `CLK_LO;
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next_spiClkOut <= 1'b0;
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next_spiDataOut <= txDataShiftReg[7];
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next_txDataShiftReg <= {txDataShiftReg[6:0], 1'b0};
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next_rxDataShiftReg <= {rxDataShiftReg[6:0], spiDataIn};
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next_clkDelayCnt <= 8'h00;
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end
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end
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`CLK_LO:
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begin
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next_clkDelayCnt <= clkDelayCnt + 1'b1;
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if ((bitCnt == 4'h8) && (txDataFull == 1'b1))
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begin
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NextState_rwSPISt <= `CLK_HI;
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next_rxDataRdySet <= 1'b1;
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next_rxDataOut <= rxDataShiftReg;
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next_txDataShiftReg <= txDataIn;
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next_bitCnt <= 3'b000;
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next_clkDelayCnt <= 8'h00;
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next_txDataFullClr <= 1'b1;
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end
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else if (bitCnt == 4'h8)
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begin
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NextState_rwSPISt <= `WT_TX_DATA;
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next_rxDataRdySet <= 1'b1;
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next_rxDataOut <= rxDataShiftReg;
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end
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else if (clkDelayCnt == clkDelay)
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begin
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NextState_rwSPISt <= `CLK_HI;
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next_spiClkOut <= 1'b1;
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next_bitCnt <= bitCnt + 1'b1;
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next_clkDelayCnt <= 8'h00;
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end
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end
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`ST_RW_WIRE:
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begin
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next_bitCnt <= 4'h0;
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next_clkDelayCnt <= 8'h00;
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next_txDataFullClr <= 1'b0;
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next_rxDataRdySet <= 1'b0;
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next_txDataShiftReg <= 8'h00;
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next_rxDataShiftReg <= 8'h00;
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next_rxDataOut <= 8'h00;
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next_spiDataOut <= 1'b0;
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next_spiClkOut <= 1'b0;
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next_txDataEmpty <= 1'b0;
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NextState_rwSPISt <= `WT_TX_DATA;
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end
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endcase
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end
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// Current State Logic (sequential)
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always @ (posedge clk)
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begin
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if (rst == 1'b1)
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CurrState_rwSPISt <= `ST_RW_WIRE;
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else
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CurrState_rwSPISt <= NextState_rwSPISt;
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end
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// Registered outputs logic
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always @ (posedge clk)
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begin
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if (rst == 1'b1)
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begin
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rxDataRdySet <= 1'b0;
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txDataEmpty <= 1'b0;
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txDataFullClr <= 1'b0;
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spiClkOut <= 1'b0;
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spiDataOut <= 1'b0;
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rxDataOut <= 8'h00;
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txDataShiftReg <= 8'h00;
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rxDataShiftReg <= 8'h00;
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bitCnt <= 4'h0;
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clkDelayCnt <= 8'h00;
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end
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else
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begin
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rxDataRdySet <= next_rxDataRdySet;
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txDataEmpty <= next_txDataEmpty;
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txDataFullClr <= next_txDataFullClr;
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spiClkOut <= next_spiClkOut;
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spiDataOut <= next_spiDataOut;
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rxDataOut <= next_rxDataOut;
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txDataShiftReg <= next_txDataShiftReg;
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rxDataShiftReg <= next_rxDataShiftReg;
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bitCnt <= next_bitCnt;
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clkDelayCnt <= next_clkDelayCnt;
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end
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end
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endmodule
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