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[/] [spimaster/] [trunk/] [RTL/] [sendCmd.v] - Blame information for rev 6

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// sendCmd.v                                           ////
////                                                              ////
//// This file is part of the spiMaster opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
////  If sendCmdReq asserted, then send command to 
////  SD card. Command consists of command byte,
////  4 data bytes, and a checksum byte. 
//// Waits for response byte from SD card
////  or times out if no response
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
 
 
module sendCmd (checkSumByte_1, checkSumByte_2, clk, cmdByte_1, cmdByte_2, dataByte1_1, dataByte1_2, dataByte2_1, dataByte2_2, dataByte3_1, dataByte3_2, dataByte4_1, dataByte4_2, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, sendCmdRdy, sendCmdReq1, sendCmdReq2, txDataEmpty, txDataFull, txDataOut, txDataWen);
input   [7:0]checkSumByte_1;
input   [7:0]checkSumByte_2;
input   clk;
input   [7:0]cmdByte_1;
input   [7:0]cmdByte_2;
input   [7:0]dataByte1_1;
input   [7:0]dataByte1_2;
input   [7:0]dataByte2_1;
input   [7:0]dataByte2_2;
input   [7:0]dataByte3_1;
input   [7:0]dataByte3_2;
input   [7:0]dataByte4_1;
input   [7:0]dataByte4_2;
input   rst;
input   [7:0]rxDataIn;
input   rxDataRdy;
input   sendCmdReq1;
input   sendCmdReq2;
input   txDataEmpty;
input   txDataFull;
output  [7:0]respByte;
output  respTout;
output  rxDataRdyClr;
output  sendCmdRdy;
output  [7:0]txDataOut;
output  txDataWen;
 
wire    [7:0]checkSumByte_1;
wire    [7:0]checkSumByte_2;
wire    clk;
wire    [7:0]cmdByte_1;
wire    [7:0]cmdByte_2;
wire    [7:0]dataByte1_1;
wire    [7:0]dataByte1_2;
wire    [7:0]dataByte2_1;
wire    [7:0]dataByte2_2;
wire    [7:0]dataByte3_1;
wire    [7:0]dataByte3_2;
wire    [7:0]dataByte4_1;
wire    [7:0]dataByte4_2;
reg     [7:0]respByte, next_respByte;
reg     respTout, next_respTout;
wire    rst;
wire    [7:0]rxDataIn;
wire    rxDataRdy;
reg     rxDataRdyClr, next_rxDataRdyClr;
reg     sendCmdRdy, next_sendCmdRdy;
wire    sendCmdReq1;
wire    sendCmdReq2;
wire    txDataEmpty;
wire    txDataFull;
reg     [7:0]txDataOut, next_txDataOut;
reg     txDataWen, next_txDataWen;
 
// diagram signals declarations
reg  [7:0]checkSumByte, next_checkSumByte;
reg  [7:0]cmdByte, next_cmdByte;
reg  [7:0]dataByte1, next_dataByte1;
reg  [7:0]dataByte2, next_dataByte2;
reg  [7:0]dataByte3, next_dataByte3;
reg  [7:0]dataByte4, next_dataByte4;
reg sendCmdReq, next_sendCmdReq;
reg  [9:0]timeOutCnt, next_timeOutCnt;
 
// BINARY ENCODED state machine: sndCmdSt
// State codes definitions:
`define CMD_D_BYTE2_FIN 5'b00000
`define CMD_D_BYTE2_ST 5'b00001
`define CMD_SEND_FF_FIN 5'b00010
`define CMD_CMD_BYTE_FIN 5'b00011
`define CMD_D_BYTE1_FIN 5'b00100
`define CMD_REQ_RESP_ST 5'b00101
`define CMD_REQ_RESP_FIN 5'b00110
`define CMD_CHK_RESP 5'b00111
`define CMD_D_BYTE1_ST 5'b01000
`define CMD_D_BYTE3_FIN 5'b01001
`define CMD_D_BYTE3_ST 5'b01010
`define CMD_D_BYTE4_FIN 5'b01011
`define CMD_D_BYTE4_ST 5'b01100
`define CMD_CS_FIN 5'b01101
`define CMD_CS_ST 5'b01110
`define CMD_SEND_FF_ST 5'b01111
`define CMD_CMD_BYTE_ST 5'b10000
`define WT_CMD 5'b10001
`define ST_S_CMD 5'b10010
`define CMD_DEL 5'b10011
 
reg [4:0]CurrState_sndCmdSt, NextState_sndCmdSt;
 
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
always @(sendCmdReq1 or sendCmdReq2 ) begin
sendCmdReq <= sendCmdReq1 | sendCmdReq2;
end
always @(posedge clk) begin
cmdByte <= cmdByte_1 | cmdByte_2;
dataByte1 <= dataByte1_1 | dataByte1_2;
dataByte2 <= dataByte2_1 | dataByte2_2;
dataByte3 <= dataByte3_1 | dataByte3_2;
dataByte4 <= dataByte4_1 | dataByte4_2;
checkSumByte <= checkSumByte_1 | checkSumByte_2;
end
 
 
// Machine: sndCmdSt
 
// NextState logic (combinatorial)
always @ (txDataFull or dataByte2 or timeOutCnt or rxDataRdy or rxDataIn or respByte or dataByte1 or dataByte3 or dataByte4 or txDataEmpty or checkSumByte or cmdByte or sendCmdReq or txDataWen or txDataOut or rxDataRdyClr or respTout or sendCmdRdy or CurrState_sndCmdSt)
begin
  NextState_sndCmdSt <= CurrState_sndCmdSt;
  // Set default values for outputs and signals
  next_txDataWen <= txDataWen;
  next_txDataOut <= txDataOut;
  next_timeOutCnt <= timeOutCnt;
  next_rxDataRdyClr <= rxDataRdyClr;
  next_respByte <= respByte;
  next_respTout <= respTout;
  next_sendCmdRdy <= sendCmdRdy;
  case (CurrState_sndCmdSt)  // synopsys parallel_case full_case
    `WT_CMD:
    begin
      next_sendCmdRdy <= 1'b1;
      if (sendCmdReq == 1'b1)
      begin
        NextState_sndCmdSt <= `CMD_SEND_FF_ST;
        next_sendCmdRdy <= 1'b0;
        next_respTout <= 1'b0;
      end
    end
    `ST_S_CMD:
    begin
      next_sendCmdRdy <= 1'b0;
      next_txDataWen <= 1'b0;
      next_txDataOut <= 8'h00;
      next_rxDataRdyClr <= 1'b0;
      next_respByte <= 8'h00;
      next_respTout <= 1'b0;
      next_timeOutCnt <= 10'h000;
      NextState_sndCmdSt <= `WT_CMD;
    end
    `CMD_D_BYTE2_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_sndCmdSt <= `CMD_D_BYTE3_ST;
    end
    `CMD_D_BYTE2_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_D_BYTE2_FIN;
        next_txDataOut <= dataByte2;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_SEND_FF_FIN:
    begin
      NextState_sndCmdSt <= `CMD_CMD_BYTE_ST;
    end
    `CMD_CMD_BYTE_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_sndCmdSt <= `CMD_D_BYTE1_ST;
    end
    `CMD_D_BYTE1_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_sndCmdSt <= `CMD_D_BYTE2_ST;
    end
    `CMD_REQ_RESP_ST:
    begin
      NextState_sndCmdSt <= `CMD_DEL;
      next_txDataOut <= 8'hff;
      next_txDataWen <= 1'b1;
      next_timeOutCnt <= timeOutCnt + 1'b1;
      next_rxDataRdyClr <= 1'b1;
    end
    `CMD_REQ_RESP_FIN:
    begin
      if (rxDataRdy == 1'b1)
      begin
        NextState_sndCmdSt <= `CMD_CHK_RESP;
        next_respByte <= rxDataIn;
      end
    end
    `CMD_CHK_RESP:
    begin
      if (timeOutCnt == 10'h200)
      begin
        NextState_sndCmdSt <= `WT_CMD;
        next_respTout <= 1'b1;
      end
      else if (respByte[7] == 1'b0)
      begin
        NextState_sndCmdSt <= `WT_CMD;
      end
      else
      begin
        NextState_sndCmdSt <= `CMD_REQ_RESP_ST;
      end
    end
    `CMD_D_BYTE1_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_D_BYTE1_FIN;
        next_txDataOut <= dataByte1;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_D_BYTE3_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_sndCmdSt <= `CMD_D_BYTE4_ST;
    end
    `CMD_D_BYTE3_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_D_BYTE3_FIN;
        next_txDataOut <= dataByte3;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_D_BYTE4_FIN:
    begin
      next_txDataWen <= 1'b0;
      NextState_sndCmdSt <= `CMD_CS_ST;
    end
    `CMD_D_BYTE4_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_D_BYTE4_FIN;
        next_txDataOut <= dataByte4;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_CS_FIN:
    begin
      next_txDataWen <= 1'b0;
      next_timeOutCnt <= 10'h000;
      if (txDataEmpty == 1'b1)
      begin
        NextState_sndCmdSt <= `CMD_REQ_RESP_ST;
      end
    end
    `CMD_CS_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_CS_FIN;
        next_txDataOut <= checkSumByte;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_SEND_FF_ST:
    begin
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_SEND_FF_FIN;
        next_txDataOut <= 8'hff;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_CMD_BYTE_ST:
    begin
      next_txDataWen <= 1'b0;
      if (txDataFull == 1'b0)
      begin
        NextState_sndCmdSt <= `CMD_CMD_BYTE_FIN;
        next_txDataOut <= cmdByte;
        next_txDataWen <= 1'b1;
      end
    end
    `CMD_DEL:
    begin
      NextState_sndCmdSt <= `CMD_REQ_RESP_FIN;
      next_txDataWen <= 1'b0;
      next_rxDataRdyClr <= 1'b0;
    end
  endcase
end
 
// Current State Logic (sequential)
always @ (posedge clk)
begin
  if (rst == 1'b1)
    CurrState_sndCmdSt <= `ST_S_CMD;
  else
    CurrState_sndCmdSt <= NextState_sndCmdSt;
end
 
// Registered outputs logic
always @ (posedge clk)
begin
  if (rst == 1'b1)
  begin
    txDataWen <= 1'b0;
    txDataOut <= 8'h00;
    rxDataRdyClr <= 1'b0;
    respByte <= 8'h00;
    respTout <= 1'b0;
    sendCmdRdy <= 1'b0;
    timeOutCnt <= 10'h000;
  end
  else
  begin
    txDataWen <= next_txDataWen;
    txDataOut <= next_txDataOut;
    rxDataRdyClr <= next_rxDataRdyClr;
    respByte <= next_respByte;
    respTout <= next_respTout;
    sendCmdRdy <= next_sendCmdRdy;
    timeOutCnt <= next_timeOutCnt;
  end
end
 
endmodule

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[/] [spimaster/] [trunk/] [RTL/] [sendCmd.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	sfielding
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// sendCmd.v ////`
5			`//// ////`
6			`//// This file is part of the spiMaster opencores effort.`
7			`//// <http://www.opencores.org/cores//> ////`
8			`//// ////`
9			`//// Module Description: ////`
10			`//// If sendCmdReq asserted, then send command to`
11			`//// SD card. Command consists of command byte,`
12			`//// 4 data bytes, and a checksum byte.`
13			`//// Waits for response byte from SD card`
14			`//// or times out if no response`
15			`//// ////`
16			`//// To Do: ////`
17			`////`
18			`//// ////`
19			`//// Author(s): ////`
20			`//// - Steve Fielding, sfielding@base2designs.com ////`
21			`//// ////`
22			`//////////////////////////////////////////////////////////////////////`
23			`//// ////`
24			`//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////`
25			`//// ////`
26			`//// This source file may be used and distributed without ////`
27			`//// restriction provided that this copyright statement is not ////`
28			`//// removed from the file and that any derivative work contains ////`
29			`//// the original copyright notice and the associated disclaimer. ////`
30			`//// ////`
31			`//// This source file is free software; you can redistribute it ////`
32			`//// and/or modify it under the terms of the GNU Lesser General ////`
33			`//// Public License as published by the Free Software Foundation; ////`
34			`//// either version 2.1 of the License, or (at your option) any ////`
35			`//// later version. ////`
36			`//// ////`
37			`//// This source is distributed in the hope that it will be ////`
38			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
39			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
40			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
41			`//// details. ////`
42			`//// ////`
43			`//// You should have received a copy of the GNU Lesser General ////`
44			`//// Public License along with this source; if not, download it ////`
45			`//// from <http://www.opencores.org/lgpl.shtml> ////`
46			`//// ////`
47			`//////////////////////////////////////////////////////////////////////`
48			`//`
49			`include "timescale.v"
50
51
52			`module sendCmd (checkSumByte_1, checkSumByte_2, clk, cmdByte_1, cmdByte_2, dataByte1_1, dataByte1_2, dataByte2_1, dataByte2_2, dataByte3_1, dataByte3_2, dataByte4_1, dataByte4_2, respByte, respTout, rst, rxDataIn, rxDataRdy, rxDataRdyClr, sendCmdRdy, sendCmdReq1, sendCmdReq2, txDataEmpty, txDataFull, txDataOut, txDataWen);`
53			`input [7:0]checkSumByte_1;`
54			`input [7:0]checkSumByte_2;`
55			`input clk;`
56			`input [7:0]cmdByte_1;`
57			`input [7:0]cmdByte_2;`
58			`input [7:0]dataByte1_1;`
59			`input [7:0]dataByte1_2;`
60			`input [7:0]dataByte2_1;`
61			`input [7:0]dataByte2_2;`
62			`input [7:0]dataByte3_1;`
63			`input [7:0]dataByte3_2;`
64			`input [7:0]dataByte4_1;`
65			`input [7:0]dataByte4_2;`
66			`input rst;`
67			`input [7:0]rxDataIn;`
68			`input rxDataRdy;`
69			`input sendCmdReq1;`
70			`input sendCmdReq2;`
71			`input txDataEmpty;`
72			`input txDataFull;`
73			`output [7:0]respByte;`
74			`output respTout;`
75			`output rxDataRdyClr;`
76			`output sendCmdRdy;`
77			`output [7:0]txDataOut;`
78			`output txDataWen;`
79
80			`wire [7:0]checkSumByte_1;`
81			`wire [7:0]checkSumByte_2;`
82			`wire clk;`
83			`wire [7:0]cmdByte_1;`
84			`wire [7:0]cmdByte_2;`
85			`wire [7:0]dataByte1_1;`
86			`wire [7:0]dataByte1_2;`
87			`wire [7:0]dataByte2_1;`
88			`wire [7:0]dataByte2_2;`
89			`wire [7:0]dataByte3_1;`
90			`wire [7:0]dataByte3_2;`
91			`wire [7:0]dataByte4_1;`
92			`wire [7:0]dataByte4_2;`
93			`reg [7:0]respByte, next_respByte;`
94			`reg respTout, next_respTout;`
95			`wire rst;`
96			`wire [7:0]rxDataIn;`
97			`wire rxDataRdy;`
98			`reg rxDataRdyClr, next_rxDataRdyClr;`
99			`reg sendCmdRdy, next_sendCmdRdy;`
100			`wire sendCmdReq1;`
101			`wire sendCmdReq2;`
102			`wire txDataEmpty;`
103			`wire txDataFull;`
104			`reg [7:0]txDataOut, next_txDataOut;`
105			`reg txDataWen, next_txDataWen;`
106
107			`// diagram signals declarations`
108			`reg [7:0]checkSumByte, next_checkSumByte;`
109			`reg [7:0]cmdByte, next_cmdByte;`
110			`reg [7:0]dataByte1, next_dataByte1;`
111			`reg [7:0]dataByte2, next_dataByte2;`
112			`reg [7:0]dataByte3, next_dataByte3;`
113			`reg [7:0]dataByte4, next_dataByte4;`
114			`reg sendCmdReq, next_sendCmdReq;`
115			`reg [9:0]timeOutCnt, next_timeOutCnt;`
116
117			`// BINARY ENCODED state machine: sndCmdSt`
118			`// State codes definitions:`
119			`define CMD_D_BYTE2_FIN 5'b00000
120			`define CMD_D_BYTE2_ST 5'b00001
121			`define CMD_SEND_FF_FIN 5'b00010
122			`define CMD_CMD_BYTE_FIN 5'b00011
123			`define CMD_D_BYTE1_FIN 5'b00100
124			`define CMD_REQ_RESP_ST 5'b00101
125			`define CMD_REQ_RESP_FIN 5'b00110
126			`define CMD_CHK_RESP 5'b00111
127			`define CMD_D_BYTE1_ST 5'b01000
128			`define CMD_D_BYTE3_FIN 5'b01001
129			`define CMD_D_BYTE3_ST 5'b01010
130			`define CMD_D_BYTE4_FIN 5'b01011
131			`define CMD_D_BYTE4_ST 5'b01100
132			`define CMD_CS_FIN 5'b01101
133			`define CMD_CS_ST 5'b01110
134			`define CMD_SEND_FF_ST 5'b01111
135			`define CMD_CMD_BYTE_ST 5'b10000
136			`define WT_CMD 5'b10001
137			`define ST_S_CMD 5'b10010
138			`define CMD_DEL 5'b10011
139
140			`reg [4:0]CurrState_sndCmdSt, NextState_sndCmdSt;`
141
142			`// Diagram actions (continuous assignments allowed only: assign ...)`
143			`// diagram ACTION`
144			`always @(sendCmdReq1 or sendCmdReq2 ) begin`
145			`sendCmdReq <= sendCmdReq1 \| sendCmdReq2;`
146			`end`
147			`always @(posedge clk) begin`
148			`cmdByte <= cmdByte_1 \| cmdByte_2;`
149			`dataByte1 <= dataByte1_1 \| dataByte1_2;`
150			`dataByte2 <= dataByte2_1 \| dataByte2_2;`
151			`dataByte3 <= dataByte3_1 \| dataByte3_2;`
152			`dataByte4 <= dataByte4_1 \| dataByte4_2;`
153			`checkSumByte <= checkSumByte_1 \| checkSumByte_2;`
154			`end`
155
156
157			`// Machine: sndCmdSt`
158
159			`// NextState logic (combinatorial)`
160			`always @ (txDataFull or dataByte2 or timeOutCnt or rxDataRdy or rxDataIn or respByte or dataByte1 or dataByte3 or dataByte4 or txDataEmpty or checkSumByte or cmdByte or sendCmdReq or txDataWen or txDataOut or rxDataRdyClr or respTout or sendCmdRdy or CurrState_sndCmdSt)`
161			`begin`
162			`NextState_sndCmdSt <= CurrState_sndCmdSt;`
163			`// Set default values for outputs and signals`
164			`next_txDataWen <= txDataWen;`
165			`next_txDataOut <= txDataOut;`
166			`next_timeOutCnt <= timeOutCnt;`
167			`next_rxDataRdyClr <= rxDataRdyClr;`
168			`next_respByte <= respByte;`
169			`next_respTout <= respTout;`
170			`next_sendCmdRdy <= sendCmdRdy;`
171			`case (CurrState_sndCmdSt) // synopsys parallel_case full_case`
172			`WT_CMD:
173			`begin`
174			`next_sendCmdRdy <= 1'b1;`
175			`if (sendCmdReq == 1'b1)`
176			`begin`
177			NextState_sndCmdSt <= `CMD_SEND_FF_ST;
178			`next_sendCmdRdy <= 1'b0;`
179			`next_respTout <= 1'b0;`
180			`end`
181			`end`
182			`ST_S_CMD:
183			`begin`
184			`next_sendCmdRdy <= 1'b0;`
185			`next_txDataWen <= 1'b0;`
186			`next_txDataOut <= 8'h00;`
187			`next_rxDataRdyClr <= 1'b0;`
188			`next_respByte <= 8'h00;`
189			`next_respTout <= 1'b0;`
190			`next_timeOutCnt <= 10'h000;`
191			NextState_sndCmdSt <= `WT_CMD;
192			`end`
193			`CMD_D_BYTE2_FIN:
194			`begin`
195			`next_txDataWen <= 1'b0;`
196			NextState_sndCmdSt <= `CMD_D_BYTE3_ST;
197			`end`
198			`CMD_D_BYTE2_ST:
199			`begin`
200			`if (txDataFull == 1'b0)`
201			`begin`
202			NextState_sndCmdSt <= `CMD_D_BYTE2_FIN;
203			`next_txDataOut <= dataByte2;`
204			`next_txDataWen <= 1'b1;`
205			`end`
206			`end`
207			`CMD_SEND_FF_FIN:
208			`begin`
209			NextState_sndCmdSt <= `CMD_CMD_BYTE_ST;
210			`end`
211			`CMD_CMD_BYTE_FIN:
212			`begin`
213			`next_txDataWen <= 1'b0;`
214			NextState_sndCmdSt <= `CMD_D_BYTE1_ST;
215			`end`
216			`CMD_D_BYTE1_FIN:
217			`begin`
218			`next_txDataWen <= 1'b0;`
219			NextState_sndCmdSt <= `CMD_D_BYTE2_ST;
220			`end`
221			`CMD_REQ_RESP_ST:
222			`begin`
223			NextState_sndCmdSt <= `CMD_DEL;
224			`next_txDataOut <= 8'hff;`
225			`next_txDataWen <= 1'b1;`
226			`next_timeOutCnt <= timeOutCnt + 1'b1;`
227			`next_rxDataRdyClr <= 1'b1;`
228			`end`
229			`CMD_REQ_RESP_FIN:
230			`begin`
231			`if (rxDataRdy == 1'b1)`
232			`begin`
233			NextState_sndCmdSt <= `CMD_CHK_RESP;
234			`next_respByte <= rxDataIn;`
235			`end`
236			`end`
237			`CMD_CHK_RESP:
238			`begin`
239			`if (timeOutCnt == 10'h200)`
240			`begin`
241			NextState_sndCmdSt <= `WT_CMD;
242			`next_respTout <= 1'b1;`
243			`end`
244			`else if (respByte[7] == 1'b0)`
245			`begin`
246			NextState_sndCmdSt <= `WT_CMD;
247			`end`
248			`else`
249			`begin`
250			NextState_sndCmdSt <= `CMD_REQ_RESP_ST;
251			`end`
252			`end`
253			`CMD_D_BYTE1_ST:
254			`begin`
255			`if (txDataFull == 1'b0)`
256			`begin`
257			NextState_sndCmdSt <= `CMD_D_BYTE1_FIN;
258			`next_txDataOut <= dataByte1;`
259			`next_txDataWen <= 1'b1;`
260			`end`
261			`end`
262			`CMD_D_BYTE3_FIN:
263			`begin`
264			`next_txDataWen <= 1'b0;`
265			NextState_sndCmdSt <= `CMD_D_BYTE4_ST;
266			`end`
267			`CMD_D_BYTE3_ST:
268			`begin`
269			`if (txDataFull == 1'b0)`
270			`begin`
271			NextState_sndCmdSt <= `CMD_D_BYTE3_FIN;
272			`next_txDataOut <= dataByte3;`
273			`next_txDataWen <= 1'b1;`
274			`end`
275			`end`
276			`CMD_D_BYTE4_FIN:
277			`begin`
278			`next_txDataWen <= 1'b0;`
279			NextState_sndCmdSt <= `CMD_CS_ST;
280			`end`
281			`CMD_D_BYTE4_ST:
282			`begin`
283			`if (txDataFull == 1'b0)`
284			`begin`
285			NextState_sndCmdSt <= `CMD_D_BYTE4_FIN;
286			`next_txDataOut <= dataByte4;`
287			`next_txDataWen <= 1'b1;`
288			`end`
289			`end`
290			`CMD_CS_FIN:
291			`begin`
292			`next_txDataWen <= 1'b0;`
293			`next_timeOutCnt <= 10'h000;`
294			`if (txDataEmpty == 1'b1)`
295			`begin`
296			NextState_sndCmdSt <= `CMD_REQ_RESP_ST;
297			`end`
298			`end`
299			`CMD_CS_ST:
300			`begin`
301			`if (txDataFull == 1'b0)`
302			`begin`
303			NextState_sndCmdSt <= `CMD_CS_FIN;
304			`next_txDataOut <= checkSumByte;`
305			`next_txDataWen <= 1'b1;`
306			`end`
307			`end`
308			`CMD_SEND_FF_ST:
309			`begin`
310			`if (txDataFull == 1'b0)`
311			`begin`
312			NextState_sndCmdSt <= `CMD_SEND_FF_FIN;
313			`next_txDataOut <= 8'hff;`
314			`next_txDataWen <= 1'b1;`
315			`end`
316			`end`
317			`CMD_CMD_BYTE_ST:
318			`begin`
319			`next_txDataWen <= 1'b0;`
320			`if (txDataFull == 1'b0)`
321			`begin`
322			NextState_sndCmdSt <= `CMD_CMD_BYTE_FIN;
323			`next_txDataOut <= cmdByte;`
324			`next_txDataWen <= 1'b1;`
325			`end`
326			`end`
327			`CMD_DEL:
328			`begin`
329			NextState_sndCmdSt <= `CMD_REQ_RESP_FIN;
330			`next_txDataWen <= 1'b0;`
331			`next_rxDataRdyClr <= 1'b0;`
332			`end`
333			`endcase`
334			`end`
335
336			`// Current State Logic (sequential)`
337			`always @ (posedge clk)`
338			`begin`
339			`if (rst == 1'b1)`
340			CurrState_sndCmdSt <= `ST_S_CMD;
341			`else`
342			`CurrState_sndCmdSt <= NextState_sndCmdSt;`
343			`end`
344
345			`// Registered outputs logic`
346			`always @ (posedge clk)`
347			`begin`
348			`if (rst == 1'b1)`
349			`begin`
350			`txDataWen <= 1'b0;`
351			`txDataOut <= 8'h00;`
352			`rxDataRdyClr <= 1'b0;`
353			`respByte <= 8'h00;`
354			`respTout <= 1'b0;`
355			`sendCmdRdy <= 1'b0;`
356			`timeOutCnt <= 10'h000;`
357			`end`
358			`else`
359			`begin`
360			`txDataWen <= next_txDataWen;`
361			`txDataOut <= next_txDataOut;`
362			`rxDataRdyClr <= next_rxDataRdyClr;`
363			`respByte <= next_respByte;`
364			`respTout <= next_respTout;`
365			`sendCmdRdy <= next_sendCmdRdy;`
366			`timeOutCnt <= next_timeOutCnt;`
367			`end`
368			`end`
369
370			`endmodule`