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sfielding |
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// spiCtrl.v ////
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//// ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Controls access to the 3 types of SPI access
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//// Direct SPI access, SD initialisation, and SD block read/write
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "spiMaster_defines.v"
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module spiCtrl (clk, readWriteSDBlockRdy, readWriteSDBlockReq, rst, rxDataRdy, rxDataRdyClr, SDInitRdy, SDInitReq, spiCS_n, spiTransCtrl, spiTransSts, spiTransType, txDataWen);
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input clk;
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input readWriteSDBlockRdy;
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input rst;
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input rxDataRdy;
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input SDInitRdy;
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input spiTransCtrl;
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input [1:0]spiTransType;
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output [1:0]readWriteSDBlockReq;
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output rxDataRdyClr;
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output SDInitReq;
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output spiCS_n;
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output spiTransSts;
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output txDataWen;
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wire clk;
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wire readWriteSDBlockRdy;
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reg [1:0]readWriteSDBlockReq, next_readWriteSDBlockReq;
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wire rst;
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wire rxDataRdy;
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reg rxDataRdyClr, next_rxDataRdyClr;
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wire SDInitRdy;
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reg SDInitReq, next_SDInitReq;
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reg spiCS_n, next_spiCS_n;
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wire spiTransCtrl;
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reg spiTransSts, next_spiTransSts;
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wire [1:0]spiTransType;
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reg txDataWen, next_txDataWen;
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// BINARY ENCODED state machine: spiCtrlSt
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// State codes definitions:
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`define ST_S_CTRL 3'b000
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`define WT_S_CTRL_REQ 3'b001
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`define WT_FIN1 3'b010
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`define DIR_ACC 3'b011
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`define INIT 3'b100
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`define WT_FIN2 3'b101
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`define RW 3'b110
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`define WT_FIN3 3'b111
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reg [2:0]CurrState_spiCtrlSt, NextState_spiCtrlSt;
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// Diagram actions (continuous assignments allowed only: assign ...)
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// diagram ACTION
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// Machine: spiCtrlSt
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// NextState logic (combinatorial)
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always @ (spiTransCtrl or rxDataRdy or spiTransType or SDInitRdy or readWriteSDBlockRdy or readWriteSDBlockReq or txDataWen or SDInitReq or rxDataRdyClr or spiTransSts or spiCS_n or CurrState_spiCtrlSt)
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begin
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NextState_spiCtrlSt <= CurrState_spiCtrlSt;
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// Set default values for outputs and signals
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next_readWriteSDBlockReq <= readWriteSDBlockReq;
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next_txDataWen <= txDataWen;
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next_SDInitReq <= SDInitReq;
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next_rxDataRdyClr <= rxDataRdyClr;
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next_spiTransSts <= spiTransSts;
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next_spiCS_n <= spiCS_n;
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case (CurrState_spiCtrlSt) // synopsys parallel_case full_case
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`ST_S_CTRL:
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begin
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next_readWriteSDBlockReq <= `NO_BLOCK_REQ;
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next_txDataWen <= 1'b0;
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next_SDInitReq <= 1'b0;
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next_rxDataRdyClr <= 1'b0;
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next_spiTransSts <= `TRANS_NOT_BUSY;
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next_spiCS_n <= 1'b1;
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NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
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end
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`WT_S_CTRL_REQ:
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begin
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next_rxDataRdyClr <= 1'b0;
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next_spiTransSts <= `TRANS_NOT_BUSY;
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if ((spiTransCtrl == `TRANS_START) && (spiTransType == `INIT_SD))
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begin
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NextState_spiCtrlSt <= `INIT;
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next_spiTransSts <= `TRANS_BUSY;
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next_SDInitReq <= 1'b1;
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end
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else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_WRITE_SD_BLOCK))
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begin
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NextState_spiCtrlSt <= `RW;
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next_spiTransSts <= `TRANS_BUSY;
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next_readWriteSDBlockReq <= `WRITE_SD_BLOCK;
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end
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else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `RW_READ_SD_BLOCK))
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begin
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NextState_spiCtrlSt <= `RW;
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next_spiTransSts <= `TRANS_BUSY;
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next_readWriteSDBlockReq <= `READ_SD_BLOCK;
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end
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else if ((spiTransCtrl == `TRANS_START) && (spiTransType == `DIRECT_ACCESS))
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begin
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NextState_spiCtrlSt <= `DIR_ACC;
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next_spiTransSts <= `TRANS_BUSY;
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next_txDataWen <= 1'b1;
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next_spiCS_n <= 1'b0;
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end
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end
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`WT_FIN1:
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begin
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if (rxDataRdy == 1'b1)
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begin
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NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
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next_rxDataRdyClr <= 1'b1;
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next_spiCS_n <= 1'b1;
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end
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end
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`DIR_ACC:
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begin
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next_txDataWen <= 1'b0;
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NextState_spiCtrlSt <= `WT_FIN1;
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end
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`INIT:
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begin
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next_SDInitReq <= 1'b0;
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NextState_spiCtrlSt <= `WT_FIN2;
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end
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`WT_FIN2:
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begin
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if (SDInitRdy == 1'b1)
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begin
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NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
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end
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end
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`RW:
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begin
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next_readWriteSDBlockReq <= `NO_BLOCK_REQ;
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NextState_spiCtrlSt <= `WT_FIN3;
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end
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`WT_FIN3:
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begin
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if (readWriteSDBlockRdy == 1'b1)
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begin
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NextState_spiCtrlSt <= `WT_S_CTRL_REQ;
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end
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end
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endcase
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end
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// Current State Logic (sequential)
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always @ (posedge clk)
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begin
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if (rst == 1'b1)
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CurrState_spiCtrlSt <= `ST_S_CTRL;
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else
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CurrState_spiCtrlSt <= NextState_spiCtrlSt;
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end
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// Registered outputs logic
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always @ (posedge clk)
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begin
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if (rst == 1'b1)
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begin
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readWriteSDBlockReq <= `NO_BLOCK_REQ;
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txDataWen <= 1'b0;
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SDInitReq <= 1'b0;
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rxDataRdyClr <= 1'b0;
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spiTransSts <= `TRANS_NOT_BUSY;
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spiCS_n <= 1'b1;
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end
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else
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begin
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readWriteSDBlockReq <= next_readWriteSDBlockReq;
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txDataWen <= next_txDataWen;
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SDInitReq <= next_SDInitReq;
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rxDataRdyClr <= next_rxDataRdyClr;
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spiTransSts <= next_spiTransSts;
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spiCS_n <= next_spiCS_n;
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end
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end
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endmodule
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