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[/] [spimaster/] [trunk/] [RTL/] [spiMaster.v] - Blame information for rev 4

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1 2 sfielding
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// spiMaster.v                                                    ////
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////                                                              ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//>                           ////
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////                                                              ////
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//// Module Description:                                          ////
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////  Top level module
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//// 
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////  
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//// 
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////                                                              ////
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//// To Do:                                                       ////
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//// 
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Steve Fielding, sfielding@base2designs.com                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from <http://www.opencores.org/lgpl.shtml>                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "spiMaster_defines.v"
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50
module spiMaster(
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  clk_i,
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  rst_i,
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  address_i,
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  data_i,
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  data_o,
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  strobe_i,
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  we_i,
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  ack_o,
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60
  // SPI logic clock
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  spiSysClk,
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63
  //SPI bus
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  spiClkOut,
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  spiDataIn,
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  spiDataOut,
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  spiCS_n
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);
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//Wishbone bus
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input clk_i;
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input rst_i;
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input [7:0] address_i;
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input [7:0] data_i;
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output [7:0] data_o;
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input strobe_i;
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input we_i;
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output ack_o;
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80
// SPI logic clock
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input spiSysClk;
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83
//SPI bus
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output spiClkOut;
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input spiDataIn;
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output spiDataOut;
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output spiCS_n;
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// local wires and regs
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wire spiSysClk;
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wire [7:0] spiClkDelayFromInitSD;
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wire rstSyncToSpiClk;
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wire [7:0] rxDataFromRWSPIWireData;
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wire rxDataRdySetFromRWSPIWireData;
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wire txDataFullFromSpiTxRxData;
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wire txDataFullClrFromRWSPIWireData;
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wire [7:0] txDataToRWSPIWireData;
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wire rxDataRdyClrFromRWSDBlock;
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wire rxDataRdyClrFromSendCmd;
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wire [7:0] rxDataFromSpiTxRxData;
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wire rxDataRdy;
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wire [7:0] txDataFromRWSDBlock;
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wire txDataWenFromRWSDBlock;
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wire [7:0] txDataFromSendCmd;
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wire txDataWenFromSendCmd;
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wire [7:0] txDataFromInitSD;
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wire txDataWenFromInitSD;
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wire [7:0] dataFromCtrlStsReg;
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wire [7:0] dataFromTxFifo;
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wire [7:0] dataFromRxFifo;
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wire [1:0] spiTransType;
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wire [7:0] spiDirectAccessTxData;
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wire [1:0] readWriteSDBlockReq;
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wire [1:0] SDWriteError;
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wire [1:0] SDReadError;
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wire [1:0] SDInitError;
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wire [7:0] cmdByteFromInitSD;
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wire [7:0] dataByte1FromInitSD;
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wire [7:0] dataByte2FromInitSD;
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wire [7:0] dataByte3FromInitSD;
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wire [7:0] dataByte4FromInitSD;
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wire [7:0] checkSumByteFromInitSD;
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wire [7:0] sendCmdRespByte;
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wire [7:0] cmdByteFromRWSDBlock;
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wire [7:0] dataByte1FromRWSDBlock;
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wire [7:0] dataByte2FromRWSDBlock;
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wire [7:0] dataByte3FromRWSDBlock;
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wire [7:0] dataByte4FromRWSDBlock;
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wire [7:0] checkSumByteFromRWSDBlock;
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wire [7:0] txFifoDataOut;
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wire [7:0] rxFifoDataIn;
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wire [31:0] SDAddr;
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wire [7:0] spiClkDelayFromCtrlStsReg;
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wire spiCS_nFromInitSD;
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wire spiCS_nFromRWSDBlock;
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wire spiCS_nFromSpiCtrl;
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138
 
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assign spiCS_n = spiCS_nFromInitSD & spiCS_nFromRWSDBlock & spiCS_nFromSpiCtrl;
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141
// -----------------------------------
142
// Instance of Module: wishBoneBI
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// -----------------------------------
144
spiMasterWishBoneBI u_spiMasterWishBoneBI(
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  .ack_o(               ack_o                 ),
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  .address(             address_i             ),
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  .clk(                 clk_i                 ),
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  .ctrlStsRegSel(       ctrlStsRegSel         ),
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  .dataFromCtrlStsReg(  dataFromCtrlStsReg    ),
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  .dataFromRxFifo(      dataFromRxFifo        ),
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  .dataFromTxFifo(      dataFromTxFifo        ),
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  .dataIn(              data_i                ),
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  .dataOut(             data_o                ),
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  .rst(                 rst_i                 ),
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  .rxFifoSel(           rxFifoSel             ),
156
  .strobe_i(            strobe_i              ),
157
  .txFifoSel(           txFifoSel             ),
158
  .writeEn(             we_i                  )
159
        );
160
 
161
// -----------------------------------
162
// Instance of Module: ctrlStsRegBI
163
// -----------------------------------
164
ctrlStsRegBI u_ctrlStsRegBI(
165
  .busClk(              clk_i                 ),
166
  .spiSysClk(           spiSysClk             ),
167
  .rstSyncToBusClkOut(  rstSyncToBusClk       ),
168
  .rstSyncToSpiClkOut(  rstSyncToSpiClk       ),
169
  .rstFromWire(         rst_i                 ),
170
  .address(             address_i             ),
171
  .strobe_i(            strobe_i              ),
172
  .dataIn(              data_i                ),
173
  .dataOut(             dataFromCtrlStsReg    ),
174
  .ctrlStsRegSel(       ctrlStsRegSel         ),
175
  .spiTransType(        spiTransType          ),
176
  .spiTransCtrl(        spiTransCtrl          ),
177
  .spiTransStatus(      spiTransSts           ),
178
  .spiDirectAccessTxData(spiDirectAccessTxData),
179
  .spiDirectAccessRxData(rxDataFromSpiTxRxData),
180
  .writeEn(             we_i                  ),
181
  .SDWriteError(        SDWriteError          ),
182
  .SDReadError(         SDReadError           ),
183
  .SDInitError(         SDInitError           ),
184
  .SDAddr(              SDAddr                ),
185
  .spiClkDelay(         spiClkDelayFromCtrlStsReg)
186
        );
187
 
188
// -----------------------------------
189
// Instance of Module: spiCtrl
190
// -----------------------------------
191
spiCtrl u_spiCtrl(
192
  .clk(                 spiSysClk             ),
193
  .rst(                 rstSyncToSpiClk       ),
194
  .SDInitReq(           SDInitReq             ),
195
  .SDInitRdy(           SDInitRdy             ),
196
  .readWriteSDBlockReq( readWriteSDBlockReq   ),
197
  .readWriteSDBlockRdy( readWriteSDBlockRdy   ),
198
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
199
  .rxDataRdyClr(        rxDataRdyClrFromSpiCtrl),
200
  .spiTransType(        spiTransType          ),
201
  .spiTransCtrl(        spiTransCtrl          ),
202
  .spiTransSts(         spiTransSts           ),
203
  .txDataWen(           txDataWenFromSpiCtrl  ),
204
  .spiCS_n(             spiCS_nFromSpiCtrl    )
205
        );
206
 
207
 
208
// -----------------------------------
209
// Instance of Module: initSD
210
// -----------------------------------
211
initSD u_initSD(
212
  .clk(                 spiSysClk             ),
213
  .rst(                 rstSyncToSpiClk       ),
214
  .SDInitReq(           SDInitReq             ),
215
  .SDInitRdy(           SDInitRdy             ),
216
  .initError(           SDInitError           ),
217
  .sendCmdReq(          sendCmdReqFromInitSD  ),
218
  .sendCmdRdy(          sendCmdRdy            ),
219
  .cmdByte(             cmdByteFromInitSD     ),
220
  .dataByte1(           dataByte1FromInitSD   ),
221
  .dataByte2(           dataByte2FromInitSD   ),
222
  .dataByte3(           dataByte3FromInitSD   ),
223
  .dataByte4(           dataByte4FromInitSD   ),
224
  .checkSumByte(        checkSumByteFromInitSD),
225
  .respByte(            sendCmdRespByte       ),
226
  .respTout(            sendCmdRespTout       ),
227
  .spiCS_n(             spiCS_nFromInitSD    ),
228
  .spiClkDelayOut(      spiClkDelayFromInitSD ),
229
  .spiClkDelayIn(       spiClkDelayFromCtrlStsReg),
230
  .txDataFull(          txDataFullFromSpiTxRxData),
231
  .txDataEmpty(         txDataEmptyFromRWSPIWireData),
232
  .txDataOut(           txDataFromInitSD      ),
233
  .txDataWen(           txDataWenFromInitSD   ),
234
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
235
  .rxDataRdyClr(        rxDataRdyClrFromInitSD)
236
        );
237
 
238
// -----------------------------------
239
// Instance of Module: readWriteSDBlock
240
// -----------------------------------
241
readWriteSDBlock u_readWriteSDBlock(
242
  .clk(                 spiSysClk             ),
243
  .rst(                 rstSyncToSpiClk       ),
244
  .readWriteSDBlockReq( readWriteSDBlockReq   ),
245
  .readWriteSDBlockRdy( readWriteSDBlockRdy   ),
246
  .cmdByte(             cmdByteFromRWSDBlock  ),
247
  .dataByte1(           dataByte1FromRWSDBlock),
248
  .dataByte2(           dataByte2FromRWSDBlock),
249
  .dataByte3(           dataByte3FromRWSDBlock),
250
  .dataByte4(           dataByte4FromRWSDBlock),
251
  .checkSumByte(        checkSumByteFromRWSDBlock),
252
  .readError(           SDReadError             ),
253
  .respByte(            sendCmdRespByte       ),
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  .respTout(            sendCmdRespTout       ),
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  .rxDataIn(            rxDataFromSpiTxRxData ),
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  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
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  .rxDataRdyClr(        rxDataRdyClrFromRWSDBlock),
258
  .sendCmdRdy(          sendCmdRdy            ),
259
  .sendCmdReq(          sendCmdReqFromRWSDBlock),
260
  .spiCS_n(             spiCS_nFromRWSDBlock ),
261
  .txDataFull(          txDataFullFromSpiTxRxData),
262
  .txDataEmpty(         txDataEmptyFromRWSPIWireData),
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  .txDataOut(           txDataFromRWSDBlock   ),
264
  .txDataWen(           txDataWenFromRWSDBlock),
265
  .txFifoData(          txFifoDataOut         ),
266
  .txFifoRen(           txFifoRE              ),
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  .rxFifoData(          rxFifoDataIn          ),
268
  .rxFifoWen(           rRxFifoWE             ),
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  .writeError(          SDWriteError          ),
270
  .blockAddr(           SDAddr                )
271
 
272
        );
273
 
274
// -----------------------------------
275
// Instance of Module: sendCmd
276
// -----------------------------------
277
sendCmd u_sendCmd(
278
  .clk(                 spiSysClk             ),
279
  .rst(                 rstSyncToSpiClk       ),
280
  .sendCmdReq1(         sendCmdReqFromInitSD  ),
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  .sendCmdReq2(         sendCmdReqFromRWSDBlock),
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  .sendCmdRdy(          sendCmdRdy            ),
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  .cmdByte_1(           cmdByteFromInitSD     ),
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  .cmdByte_2(           cmdByteFromRWSDBlock  ),
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  .dataByte1_1(         dataByte1FromInitSD   ),
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  .dataByte1_2(         dataByte1FromRWSDBlock),
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  .dataByte2_1(         dataByte2FromInitSD   ),
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  .dataByte2_2(         dataByte2FromRWSDBlock),
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  .dataByte3_1(         dataByte3FromInitSD   ),
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  .dataByte3_2(         dataByte3FromRWSDBlock),
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  .dataByte4_1(         dataByte4FromInitSD   ),
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  .dataByte4_2(         dataByte4FromRWSDBlock),
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  .checkSumByte_1(      checkSumByteFromInitSD),
294
  .checkSumByte_2(      checkSumByteFromRWSDBlock),
295
  .respByte(            sendCmdRespByte       ),
296
  .respTout(            sendCmdRespTout       ),
297
  .rxDataIn(            rxDataFromSpiTxRxData ),
298
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
299
  .rxDataRdyClr(        rxDataRdyClrFromSendCmd),
300
  .txDataFull(          txDataFullFromSpiTxRxData),
301
  .txDataEmpty(         txDataEmptyFromRWSPIWireData),
302
  .txDataOut(           txDataFromSendCmd     ),
303
  .txDataWen(           txDataWenFromSendCmd  )
304
        );
305
 
306
// -----------------------------------
307
// Instance of Module: spiTxRxData
308
// -----------------------------------
309
spiTxRxData u_spiTxRxData(
310
  .clk(                 spiSysClk             ),
311
  .rst(                 rstSyncToSpiClk       ),
312
  .rx1DataRdyClr(       rxDataRdyClrFromRWSDBlock),
313
  .rx2DataRdyClr(       rxDataRdyClrFromSendCmd),
314
  .rx3DataRdyClr(       rxDataRdyClrFromInitSD),
315
  .rx4DataRdyClr(       rxDataRdyClrFromSpiCtrl),
316
  .rxDataIn(            rxDataFromRWSPIWireData),
317
  .rxDataOut(           rxDataFromSpiTxRxData ),
318
  .rxDataRdy(           rxDataRdyFromSpiTxRxData),
319
  .rxDataRdySet(        rxDataRdySetFromRWSPIWireData),
320
  .tx1DataIn(           txDataFromRWSDBlock   ),
321
  .tx1DataWEn(          txDataWenFromRWSDBlock),
322
  .tx2DataIn(           txDataFromSendCmd     ),
323
  .tx2DataWEn(          txDataWenFromSendCmd  ),
324
  .tx3DataIn(           txDataFromInitSD      ),
325
  .tx3DataWEn(          txDataWenFromInitSD   ),
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  .tx4DataIn(           spiDirectAccessTxData ),
327
  .tx4DataWEn(          txDataWenFromSpiCtrl  ),
328
  .txDataFull(          txDataFullFromSpiTxRxData),
329
  .txDataFullClr(       txDataFullClrFromRWSPIWireData),
330
  .txDataOut(           txDataToRWSPIWireData )
331
        );
332
 
333
// -----------------------------------
334
// Instance of Module: readWriteSPIWireData
335
// -----------------------------------
336
readWriteSPIWireData u_readWriteSPIWireData(
337
  .clk(                 spiSysClk             ),
338
  .clkDelay(            spiClkDelayFromInitSD           ),
339
  .rst(                 rstSyncToSpiClk       ),
340
  .rxDataOut(           rxDataFromRWSPIWireData),
341
  .rxDataRdySet(        rxDataRdySetFromRWSPIWireData),
342
  .spiClkOut(           spiClkOut             ),
343
  .spiDataIn(           spiDataIn             ),
344
  .spiDataOut(          spiDataOut            ),
345
  .txDataFull(          txDataFullFromSpiTxRxData),
346
  .txDataFullClr(       txDataFullClrFromRWSPIWireData),
347
  .txDataIn(            txDataToRWSPIWireData ),
348
  .txDataEmpty(         txDataEmptyFromRWSPIWireData)
349
        );
350
 
351
sm_TxFifo #(`TX_FIFO_DEPTH, `TX_FIFO_ADDR_WIDTH) u_sm_txFifo (
352
  .spiSysClk(spiSysClk),
353
  .busClk(clk_i),
354
  .rstSyncToBusClk(rstSyncToBusClk),
355
  .rstSyncToSpiClk(rstSyncToSpiClk),
356
  .fifoREn(txFifoRE),
357
  .fifoEmpty(hostTxFifoEmpty),
358
  .busAddress(address_i[2:0]),
359
  .busWriteEn(we_i),
360
  .busStrobe_i(strobe_i),
361
  .busFifoSelect(txFifoSel),
362
  .busDataIn(data_i),
363
  .busDataOut(dataFromTxFifo),
364
  .fifoDataOut(txFifoDataOut) );
365
 
366
 
367
sm_RxFifo #(`RX_FIFO_DEPTH, `RX_FIFO_ADDR_WIDTH) u_sm_rxFifo(
368
  .spiSysClk(spiSysClk),
369
  .busClk(clk_i),
370
  .rstSyncToBusClk(rstSyncToBusClk),
371
  .rstSyncToSpiClk(rstSyncToSpiClk),
372
  .fifoWEn(rRxFifoWE),
373
  .fifoFull(hostRxFifoFull),
374
  .busAddress(address_i[2:0]),
375
  .busWriteEn(we_i),
376
  .busStrobe_i(strobe_i),
377
  .busFifoSelect(rxFifoSel),
378
  .busDataIn(data_i),
379
  .busDataOut(dataFromRxFifo),
380
  .fifoDataIn(rxFifoDataIn)  );
381
 
382
endmodule
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