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sfielding |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// spiMaster.v ////
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//// ////
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//// This file is part of the spiMaster opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// Top level module
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////
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////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "spiMaster_defines.v"
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module spiMaster(
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clk_i,
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rst_i,
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address_i,
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data_i,
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data_o,
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strobe_i,
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we_i,
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ack_o,
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// SPI logic clock
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spiSysClk,
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//SPI bus
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spiClkOut,
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spiDataIn,
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spiDataOut,
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spiCS_n
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);
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//Wishbone bus
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input clk_i;
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input rst_i;
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input [7:0] address_i;
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input [7:0] data_i;
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output [7:0] data_o;
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input strobe_i;
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input we_i;
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output ack_o;
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// SPI logic clock
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input spiSysClk;
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//SPI bus
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output spiClkOut;
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input spiDataIn;
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output spiDataOut;
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output spiCS_n;
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// local wires and regs
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wire spiSysClk;
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wire [7:0] spiClkDelayFromInitSD;
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wire rstSyncToSpiClk;
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wire [7:0] rxDataFromRWSPIWireData;
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wire rxDataRdySetFromRWSPIWireData;
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wire txDataFullFromSpiTxRxData;
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wire txDataFullClrFromRWSPIWireData;
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wire [7:0] txDataToRWSPIWireData;
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wire rxDataRdyClrFromRWSDBlock;
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wire rxDataRdyClrFromSendCmd;
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wire [7:0] rxDataFromSpiTxRxData;
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wire rxDataRdy;
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wire [7:0] txDataFromRWSDBlock;
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wire txDataWenFromRWSDBlock;
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wire [7:0] txDataFromSendCmd;
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wire txDataWenFromSendCmd;
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wire [7:0] txDataFromInitSD;
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wire txDataWenFromInitSD;
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wire [7:0] dataFromCtrlStsReg;
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wire [7:0] dataFromTxFifo;
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wire [7:0] dataFromRxFifo;
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wire [1:0] spiTransType;
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wire [7:0] spiDirectAccessTxData;
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wire [1:0] readWriteSDBlockReq;
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wire [1:0] SDWriteError;
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wire [1:0] SDReadError;
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wire [1:0] SDInitError;
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wire [7:0] cmdByteFromInitSD;
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wire [7:0] dataByte1FromInitSD;
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wire [7:0] dataByte2FromInitSD;
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wire [7:0] dataByte3FromInitSD;
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wire [7:0] dataByte4FromInitSD;
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wire [7:0] checkSumByteFromInitSD;
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wire [7:0] sendCmdRespByte;
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wire [7:0] cmdByteFromRWSDBlock;
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wire [7:0] dataByte1FromRWSDBlock;
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wire [7:0] dataByte2FromRWSDBlock;
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wire [7:0] dataByte3FromRWSDBlock;
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wire [7:0] dataByte4FromRWSDBlock;
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wire [7:0] checkSumByteFromRWSDBlock;
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wire [7:0] txFifoDataOut;
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wire [7:0] rxFifoDataIn;
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wire [31:0] SDAddr;
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wire [7:0] spiClkDelayFromCtrlStsReg;
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wire spiCS_nFromInitSD;
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wire spiCS_nFromRWSDBlock;
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wire spiCS_nFromSpiCtrl;
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assign spiCS_n = spiCS_nFromInitSD & spiCS_nFromRWSDBlock & spiCS_nFromSpiCtrl;
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// -----------------------------------
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// Instance of Module: wishBoneBI
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// -----------------------------------
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spiMasterWishBoneBI u_spiMasterWishBoneBI(
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.ack_o( ack_o ),
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.address( address_i ),
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.clk( clk_i ),
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.ctrlStsRegSel( ctrlStsRegSel ),
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.dataFromCtrlStsReg( dataFromCtrlStsReg ),
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.dataFromRxFifo( dataFromRxFifo ),
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.dataFromTxFifo( dataFromTxFifo ),
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.dataIn( data_i ),
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.dataOut( data_o ),
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.rst( rst_i ),
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.rxFifoSel( rxFifoSel ),
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.strobe_i( strobe_i ),
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.txFifoSel( txFifoSel ),
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.writeEn( we_i )
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);
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// -----------------------------------
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// Instance of Module: ctrlStsRegBI
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// -----------------------------------
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ctrlStsRegBI u_ctrlStsRegBI(
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.busClk( clk_i ),
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.spiSysClk( spiSysClk ),
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.rstSyncToBusClkOut( rstSyncToBusClk ),
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.rstSyncToSpiClkOut( rstSyncToSpiClk ),
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.rstFromWire( rst_i ),
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.address( address_i ),
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.strobe_i( strobe_i ),
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.dataIn( data_i ),
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.dataOut( dataFromCtrlStsReg ),
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.ctrlStsRegSel( ctrlStsRegSel ),
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.spiTransType( spiTransType ),
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.spiTransCtrl( spiTransCtrl ),
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.spiTransStatus( spiTransSts ),
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.spiDirectAccessTxData(spiDirectAccessTxData),
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.spiDirectAccessRxData(rxDataFromSpiTxRxData),
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.writeEn( we_i ),
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.SDWriteError( SDWriteError ),
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.SDReadError( SDReadError ),
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.SDInitError( SDInitError ),
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.SDAddr( SDAddr ),
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.spiClkDelay( spiClkDelayFromCtrlStsReg)
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);
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// -----------------------------------
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// Instance of Module: spiCtrl
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// -----------------------------------
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spiCtrl u_spiCtrl(
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.clk( spiSysClk ),
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.rst( rstSyncToSpiClk ),
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.SDInitReq( SDInitReq ),
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.SDInitRdy( SDInitRdy ),
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.readWriteSDBlockReq( readWriteSDBlockReq ),
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.readWriteSDBlockRdy( readWriteSDBlockRdy ),
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.rxDataRdy( rxDataRdyFromSpiTxRxData),
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.rxDataRdyClr( rxDataRdyClrFromSpiCtrl),
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.spiTransType( spiTransType ),
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.spiTransCtrl( spiTransCtrl ),
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.spiTransSts( spiTransSts ),
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.txDataWen( txDataWenFromSpiCtrl ),
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.spiCS_n( spiCS_nFromSpiCtrl )
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);
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// -----------------------------------
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// Instance of Module: initSD
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// -----------------------------------
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initSD u_initSD(
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.clk( spiSysClk ),
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.rst( rstSyncToSpiClk ),
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.SDInitReq( SDInitReq ),
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.SDInitRdy( SDInitRdy ),
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.initError( SDInitError ),
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.sendCmdReq( sendCmdReqFromInitSD ),
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.sendCmdRdy( sendCmdRdy ),
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.cmdByte( cmdByteFromInitSD ),
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.dataByte1( dataByte1FromInitSD ),
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.dataByte2( dataByte2FromInitSD ),
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.dataByte3( dataByte3FromInitSD ),
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.dataByte4( dataByte4FromInitSD ),
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.checkSumByte( checkSumByteFromInitSD),
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.respByte( sendCmdRespByte ),
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.respTout( sendCmdRespTout ),
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.spiCS_n( spiCS_nFromInitSD ),
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.spiClkDelayOut( spiClkDelayFromInitSD ),
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.spiClkDelayIn( spiClkDelayFromCtrlStsReg),
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.txDataFull( txDataFullFromSpiTxRxData),
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.txDataEmpty( txDataEmptyFromRWSPIWireData),
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.txDataOut( txDataFromInitSD ),
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.txDataWen( txDataWenFromInitSD ),
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.rxDataRdy( rxDataRdyFromSpiTxRxData),
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.rxDataRdyClr( rxDataRdyClrFromInitSD)
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);
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// -----------------------------------
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// Instance of Module: readWriteSDBlock
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// -----------------------------------
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readWriteSDBlock u_readWriteSDBlock(
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.clk( spiSysClk ),
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.rst( rstSyncToSpiClk ),
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.readWriteSDBlockReq( readWriteSDBlockReq ),
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.readWriteSDBlockRdy( readWriteSDBlockRdy ),
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.cmdByte( cmdByteFromRWSDBlock ),
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.dataByte1( dataByte1FromRWSDBlock),
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.dataByte2( dataByte2FromRWSDBlock),
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.dataByte3( dataByte3FromRWSDBlock),
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.dataByte4( dataByte4FromRWSDBlock),
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.checkSumByte( checkSumByteFromRWSDBlock),
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.readError( SDReadError ),
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.respByte( sendCmdRespByte ),
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.respTout( sendCmdRespTout ),
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.rxDataIn( rxDataFromSpiTxRxData ),
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.rxDataRdy( rxDataRdyFromSpiTxRxData),
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.rxDataRdyClr( rxDataRdyClrFromRWSDBlock),
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.sendCmdRdy( sendCmdRdy ),
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.sendCmdReq( sendCmdReqFromRWSDBlock),
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.spiCS_n( spiCS_nFromRWSDBlock ),
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.txDataFull( txDataFullFromSpiTxRxData),
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.txDataEmpty( txDataEmptyFromRWSPIWireData),
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.txDataOut( txDataFromRWSDBlock ),
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.txDataWen( txDataWenFromRWSDBlock),
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.txFifoData( txFifoDataOut ),
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.txFifoRen( txFifoRE ),
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.rxFifoData( rxFifoDataIn ),
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.rxFifoWen( rRxFifoWE ),
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.writeError( SDWriteError ),
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.blockAddr( SDAddr )
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);
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// -----------------------------------
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// Instance of Module: sendCmd
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// -----------------------------------
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sendCmd u_sendCmd(
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.clk( spiSysClk ),
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.rst( rstSyncToSpiClk ),
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.sendCmdReq1( sendCmdReqFromInitSD ),
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.sendCmdReq2( sendCmdReqFromRWSDBlock),
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.sendCmdRdy( sendCmdRdy ),
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.cmdByte_1( cmdByteFromInitSD ),
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.cmdByte_2( cmdByteFromRWSDBlock ),
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.dataByte1_1( dataByte1FromInitSD ),
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.dataByte1_2( dataByte1FromRWSDBlock),
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.dataByte2_1( dataByte2FromInitSD ),
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.dataByte2_2( dataByte2FromRWSDBlock),
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.dataByte3_1( dataByte3FromInitSD ),
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.dataByte3_2( dataByte3FromRWSDBlock),
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.dataByte4_1( dataByte4FromInitSD ),
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.dataByte4_2( dataByte4FromRWSDBlock),
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.checkSumByte_1( checkSumByteFromInitSD),
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.checkSumByte_2( checkSumByteFromRWSDBlock),
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.respByte( sendCmdRespByte ),
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.respTout( sendCmdRespTout ),
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.rxDataIn( rxDataFromSpiTxRxData ),
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.rxDataRdy( rxDataRdyFromSpiTxRxData),
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.rxDataRdyClr( rxDataRdyClrFromSendCmd),
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.txDataFull( txDataFullFromSpiTxRxData),
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.txDataEmpty( txDataEmptyFromRWSPIWireData),
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.txDataOut( txDataFromSendCmd ),
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.txDataWen( txDataWenFromSendCmd )
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);
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// -----------------------------------
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// Instance of Module: spiTxRxData
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// -----------------------------------
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spiTxRxData u_spiTxRxData(
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.clk( spiSysClk ),
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.rst( rstSyncToSpiClk ),
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.rx1DataRdyClr( rxDataRdyClrFromRWSDBlock),
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.rx2DataRdyClr( rxDataRdyClrFromSendCmd),
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.rx3DataRdyClr( rxDataRdyClrFromInitSD),
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.rx4DataRdyClr( rxDataRdyClrFromSpiCtrl),
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.rxDataIn( rxDataFromRWSPIWireData),
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.rxDataOut( rxDataFromSpiTxRxData ),
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.rxDataRdy( rxDataRdyFromSpiTxRxData),
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.rxDataRdySet( rxDataRdySetFromRWSPIWireData),
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.tx1DataIn( txDataFromRWSDBlock ),
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|
|
.tx1DataWEn( txDataWenFromRWSDBlock),
|
| 322 |
|
|
.tx2DataIn( txDataFromSendCmd ),
|
| 323 |
|
|
.tx2DataWEn( txDataWenFromSendCmd ),
|
| 324 |
|
|
.tx3DataIn( txDataFromInitSD ),
|
| 325 |
|
|
.tx3DataWEn( txDataWenFromInitSD ),
|
| 326 |
|
|
.tx4DataIn( spiDirectAccessTxData ),
|
| 327 |
|
|
.tx4DataWEn( txDataWenFromSpiCtrl ),
|
| 328 |
|
|
.txDataFull( txDataFullFromSpiTxRxData),
|
| 329 |
|
|
.txDataFullClr( txDataFullClrFromRWSPIWireData),
|
| 330 |
|
|
.txDataOut( txDataToRWSPIWireData )
|
| 331 |
|
|
);
|
| 332 |
|
|
|
| 333 |
|
|
// -----------------------------------
|
| 334 |
|
|
// Instance of Module: readWriteSPIWireData
|
| 335 |
|
|
// -----------------------------------
|
| 336 |
|
|
readWriteSPIWireData u_readWriteSPIWireData(
|
| 337 |
|
|
.clk( spiSysClk ),
|
| 338 |
|
|
.clkDelay( spiClkDelayFromInitSD ),
|
| 339 |
|
|
.rst( rstSyncToSpiClk ),
|
| 340 |
|
|
.rxDataOut( rxDataFromRWSPIWireData),
|
| 341 |
|
|
.rxDataRdySet( rxDataRdySetFromRWSPIWireData),
|
| 342 |
|
|
.spiClkOut( spiClkOut ),
|
| 343 |
|
|
.spiDataIn( spiDataIn ),
|
| 344 |
|
|
.spiDataOut( spiDataOut ),
|
| 345 |
|
|
.txDataFull( txDataFullFromSpiTxRxData),
|
| 346 |
|
|
.txDataFullClr( txDataFullClrFromRWSPIWireData),
|
| 347 |
|
|
.txDataIn( txDataToRWSPIWireData ),
|
| 348 |
|
|
.txDataEmpty( txDataEmptyFromRWSPIWireData)
|
| 349 |
|
|
);
|
| 350 |
|
|
|
| 351 |
|
|
sm_TxFifo #(`TX_FIFO_DEPTH, `TX_FIFO_ADDR_WIDTH) u_sm_txFifo (
|
| 352 |
|
|
.spiSysClk(spiSysClk),
|
| 353 |
|
|
.busClk(clk_i),
|
| 354 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 355 |
|
|
.rstSyncToSpiClk(rstSyncToSpiClk),
|
| 356 |
|
|
.fifoREn(txFifoRE),
|
| 357 |
|
|
.fifoEmpty(hostTxFifoEmpty),
|
| 358 |
|
|
.busAddress(address_i[2:0]),
|
| 359 |
|
|
.busWriteEn(we_i),
|
| 360 |
|
|
.busStrobe_i(strobe_i),
|
| 361 |
|
|
.busFifoSelect(txFifoSel),
|
| 362 |
|
|
.busDataIn(data_i),
|
| 363 |
|
|
.busDataOut(dataFromTxFifo),
|
| 364 |
|
|
.fifoDataOut(txFifoDataOut) );
|
| 365 |
|
|
|
| 366 |
|
|
|
| 367 |
|
|
sm_RxFifo #(`RX_FIFO_DEPTH, `RX_FIFO_ADDR_WIDTH) u_sm_rxFifo(
|
| 368 |
|
|
.spiSysClk(spiSysClk),
|
| 369 |
|
|
.busClk(clk_i),
|
| 370 |
|
|
.rstSyncToBusClk(rstSyncToBusClk),
|
| 371 |
|
|
.rstSyncToSpiClk(rstSyncToSpiClk),
|
| 372 |
|
|
.fifoWEn(rRxFifoWE),
|
| 373 |
|
|
.fifoFull(hostRxFifoFull),
|
| 374 |
|
|
.busAddress(address_i[2:0]),
|
| 375 |
|
|
.busWriteEn(we_i),
|
| 376 |
|
|
.busStrobe_i(strobe_i),
|
| 377 |
|
|
.busFifoSelect(rxFifoSel),
|
| 378 |
|
|
.busDataIn(data_i),
|
| 379 |
|
|
.busDataOut(dataFromRxFifo),
|
| 380 |
|
|
.fifoDataIn(rxFifoDataIn) );
|
| 381 |
|
|
|
| 382 |
|
|
endmodule
|
| 383 |
|
|
|
