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[/] [spimaster/] [trunk/] [RTL/] [spiMaster_defines.v] - Blame information for rev 4

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// ------------------------ spiMaster_defines.v ----------------------
// Version 0.0 - April 2008. Created
// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
//               spiSysClk. Fixed bug in bus accessible reset. Changed names of
//               fifo related modules to avoid conflict with other IP cores.
// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
//               in wb_ack. Fixed file headers, and added description
// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data
//               from the SPI bus on the rising edge of SCLK. This increases the
//               tsetup timing margin when reading SPI data. It turns out that the timing
//               was marginal for some SD cards when using a 24Mhz SPI clock.
//               Problem was exacerbated by the fact that the design prevents the 
//               final SPI interface Flipflops being pushed into the IO blocks.
 
`define SPI_MASTER_VERSION_NUM 8'h12
`define SPI_SYS_CLK_48MHZ
//`define SPI_SYS_CLK_30MHZ
 
//memoryMap
`define CTRL_STS_REG_BASE 8'h00
`define RX_FIFO_BASE 8'h10
`define TX_FIFO_BASE 8'h20
`define ADDRESS_DECODE_MASK 8'hf0
`define SPI_MASTER_VERSION_REG 8'h00
`define SPI_MASTER_CONTROL_REG 8'h01
`define TRANS_TYPE_REG 8'h02
`define TRANS_CTRL_REG 8'h03
`define TRANS_STS_REG 8'h04
`define TRANS_ERROR_REG 8'h05
`define DIRECT_ACCESS_DATA_REG 8'h06
`define SD_ADDR_7_0_REG 8'h07
`define SD_ADDR_15_8_REG 8'h08
`define SD_ADDR_23_16_REG 8'h09
`define SD_ADDR_31_24_REG 8'h0a
`define SPI_CLK_DEL_REG 8'h0b
 
 
//FifoAddresses
`define FIFO_DATA_REG 3'b000
`define FIFO_STATUS_REG 3'b001
`define FIFO_DATA_COUNT_MSB 3'b010
`define FIFO_DATA_COUNT_LSB 3'b011
`define FIFO_CONTROL_REG 3'b100
 
 
`ifdef SIM_COMPILE
`define SLOW_SPI_CLK 8'h2
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h001
`define TWO_FIFTY_MS 12'h001
`define ONE_HUNDRED_MS 12'h00c
`else //not SIM_COMPILE
 
`ifdef SPI_SYS_CLK_48MHZ
 
// --------------- spiSysClk = 48MHz
// if you change the clock frequency you will need to change these constants
 
// SLOW_SPI_CLK controls the SPI clock at start up.
// should be aiming for 400KHz
// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1
`define SLOW_SPI_CLK 8'h3b
// controls the SPI clock after init is complete.
// should be aiming for 24MHz ?
// controls the SPI clock after init is complete.
// should be aiming for 24MHz ?
// if spiSysClk >= 48MHz
// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1
// else FAST_SPI_CLK = 0
`define FAST_SPI_CLK 8'h00
// TWO_MS = ((2mS * spiSysClk) / 256) - 1
`define TWO_MS 10'h177
// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1
`define TWO_FIFTY_MS 12'h0b6
// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1
`define ONE_HUNDRED_MS 12'h048
 
`else //not SPI_SYS_CLK_48MHZ
 
`ifdef SPI_SYS_CLK_30MHZ
// --------------- spiSysClk = 30MHz
`define SLOW_SPI_CLK 8'h24
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h0e9
`define TWO_FIFTY_MS 12'h071
`define ONE_HUNDRED_MS 12'h02c
 
`endif //SPI_SYS_CLK_30MHZ
`endif //SPI_SYS_CLK_48MHZ
`endif //SIM_COMPILE
 
 
 
`ifdef SIM_COMPILE
`define SD_INIT_START_SEQ_LEN 8'h03
`define MAX_8_BIT 8'h08
`else
`define SD_INIT_START_SEQ_LEN 8'ha0
`define MAX_8_BIT 8'hff
`endif
 
 
`define WR_RESP_TOUT 12'hf00
 
`define NO_BLOCK_REQ 2'b00
`define WRITE_SD_BLOCK 2'b01
`define READ_SD_BLOCK 2'b10
 
`define READ_NO_ERROR 2'b00
`define READ_CMD_ERROR 2'b01
`define READ_TOKEN_ERROR 2'b10
 
`define WRITE_NO_ERROR 2'b00
`define WRITE_CMD_ERROR 2'b01
`define WRITE_DATA_ERROR 2'b10
`define WRITE_BUSY_ERROR 2'b11
 
 
`define TRANS_NOT_BUSY 1'b0
`define TRANS_BUSY 1'b1
 
`define TRANS_START 1'b1
`define TRANS_STOP 1'b0
 
`define DIRECT_ACCESS 2'b00
`define INIT_SD 2'b01
`define RW_READ_SD_BLOCK 2'b10
`define RW_WRITE_SD_BLOCK 2'b11
 
`define INIT_NO_ERROR 2'b00
`define INIT_CMD0_ERROR 2'b01
`define INIT_CMD1_ERROR 2'b10
 
`define TX_FIFO_DEPTH 512
`define TX_FIFO_ADDR_WIDTH 9
`define RX_FIFO_DEPTH 512
`define RX_FIFO_ADDR_WIDTH 9
 

Line No.	Rev	Author	Line
1	2	sfielding	`// ------------------------ spiMaster_defines.v ----------------------`
2			`// Version 0.0 - April 2008. Created`
3			`// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and`
4			`// spiSysClk. Fixed bug in bus accessible reset. Changed names of`
5			`// fifo related modules to avoid conflict with other IP cores.`
6			`// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug`
7			`// in wb_ack. Fixed file headers, and added description`
8	3	sfielding	`// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data`
9			`// from the SPI bus on the rising edge of SCLK. This increases the`
10			`// tsetup timing margin when reading SPI data. It turns out that the timing`
11			`// was marginal for some SD cards when using a 24Mhz SPI clock.`
12			`// Problem was exacerbated by the fact that the design prevents the`
13			`// final SPI interface Flipflops being pushed into the IO blocks.`
14	2	sfielding
15	3	sfielding	`define SPI_MASTER_VERSION_NUM 8'h12
16	2	sfielding	`define SPI_SYS_CLK_48MHZ
17			//`define SPI_SYS_CLK_30MHZ
18
19			`//memoryMap`
20			`define CTRL_STS_REG_BASE 8'h00
21			`define RX_FIFO_BASE 8'h10
22			`define TX_FIFO_BASE 8'h20
23			`define ADDRESS_DECODE_MASK 8'hf0
24			`define SPI_MASTER_VERSION_REG 8'h00
25			`define SPI_MASTER_CONTROL_REG 8'h01
26			`define TRANS_TYPE_REG 8'h02
27			`define TRANS_CTRL_REG 8'h03
28			`define TRANS_STS_REG 8'h04
29			`define TRANS_ERROR_REG 8'h05
30			`define DIRECT_ACCESS_DATA_REG 8'h06
31			`define SD_ADDR_7_0_REG 8'h07
32			`define SD_ADDR_15_8_REG 8'h08
33			`define SD_ADDR_23_16_REG 8'h09
34			`define SD_ADDR_31_24_REG 8'h0a
35			`define SPI_CLK_DEL_REG 8'h0b
36
37
38			`//FifoAddresses`
39			`define FIFO_DATA_REG 3'b000
40			`define FIFO_STATUS_REG 3'b001
41			`define FIFO_DATA_COUNT_MSB 3'b010
42			`define FIFO_DATA_COUNT_LSB 3'b011
43			`define FIFO_CONTROL_REG 3'b100
44
45
46			`ifdef SIM_COMPILE
47			`define SLOW_SPI_CLK 8'h2
48			`define FAST_SPI_CLK 8'h00
49			`define TWO_MS 10'h001
50			`define TWO_FIFTY_MS 12'h001
51			`define ONE_HUNDRED_MS 12'h00c
52			`else //not SIM_COMPILE
53
54			`ifdef SPI_SYS_CLK_48MHZ
55
56			`// --------------- spiSysClk = 48MHz`
57			`// if you change the clock frequency you will need to change these constants`
58
59			`// SLOW_SPI_CLK controls the SPI clock at start up.`
60			`// should be aiming for 400KHz`
61			`// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1`
62			`define SLOW_SPI_CLK 8'h3b
63			`// controls the SPI clock after init is complete.`
64			`// should be aiming for 24MHz ?`
65			`// controls the SPI clock after init is complete.`
66			`// should be aiming for 24MHz ?`
67			`// if spiSysClk >= 48MHz`
68			`// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1`
69			`// else FAST_SPI_CLK = 0`
70			`define FAST_SPI_CLK 8'h00
71			`// TWO_MS = ((2mS * spiSysClk) / 256) - 1`
72			`define TWO_MS 10'h177
73			`// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1`
74			`define TWO_FIFTY_MS 12'h0b6
75			`// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1`
76			`define ONE_HUNDRED_MS 12'h048
77
78			`else //not SPI_SYS_CLK_48MHZ
79
80			`ifdef SPI_SYS_CLK_30MHZ
81			`// --------------- spiSysClk = 30MHz`
82			`define SLOW_SPI_CLK 8'h24
83			`define FAST_SPI_CLK 8'h00
84			`define TWO_MS 10'h0e9
85			`define TWO_FIFTY_MS 12'h071
86			`define ONE_HUNDRED_MS 12'h02c
87
88			`endif //SPI_SYS_CLK_30MHZ
89			`endif //SPI_SYS_CLK_48MHZ
90			`endif //SIM_COMPILE
91
92
93
94			`ifdef SIM_COMPILE
95			`define SD_INIT_START_SEQ_LEN 8'h03
96			`define MAX_8_BIT 8'h08
97			`else
98			`define SD_INIT_START_SEQ_LEN 8'ha0
99			`define MAX_8_BIT 8'hff
100			`endif
101
102
103			`define WR_RESP_TOUT 12'hf00
104
105			`define NO_BLOCK_REQ 2'b00
106			`define WRITE_SD_BLOCK 2'b01
107			`define READ_SD_BLOCK 2'b10
108
109			`define READ_NO_ERROR 2'b00
110			`define READ_CMD_ERROR 2'b01
111			`define READ_TOKEN_ERROR 2'b10
112
113			`define WRITE_NO_ERROR 2'b00
114			`define WRITE_CMD_ERROR 2'b01
115			`define WRITE_DATA_ERROR 2'b10
116			`define WRITE_BUSY_ERROR 2'b11
117
118
119			`define TRANS_NOT_BUSY 1'b0
120			`define TRANS_BUSY 1'b1
121
122			`define TRANS_START 1'b1
123			`define TRANS_STOP 1'b0
124
125			`define DIRECT_ACCESS 2'b00
126			`define INIT_SD 2'b01
127			`define RW_READ_SD_BLOCK 2'b10
128			`define RW_WRITE_SD_BLOCK 2'b11
129
130			`define INIT_NO_ERROR 2'b00
131			`define INIT_CMD0_ERROR 2'b01
132			`define INIT_CMD1_ERROR 2'b10
133
134			`define TX_FIFO_DEPTH 512
135			`define TX_FIFO_ADDR_WIDTH 9
136			`define RX_FIFO_DEPTH 512
137			`define RX_FIFO_ADDR_WIDTH 9
138

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[/] [spimaster/] [trunk/] [RTL/] [spiMaster_defines.v] - Blame information for rev 4