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[/] [spimaster/] [trunk/] [RTL/] [spiMaster_defines.v] - Blame information for rev 2

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// ------------------------ spiMaster_defines.v ----------------------
// Version 0.0 - April 2008. Created
// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
//               spiSysClk. Fixed bug in bus accessible reset. Changed names of
//               fifo related modules to avoid conflict with other IP cores.
// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
//               in wb_ack. Fixed file headers, and added description
 
`define SPI_MASTER_VERSION_NUM 8'h11
`define SPI_SYS_CLK_48MHZ
//`define SPI_SYS_CLK_30MHZ
 
//memoryMap
`define CTRL_STS_REG_BASE 8'h00
`define RX_FIFO_BASE 8'h10
`define TX_FIFO_BASE 8'h20
`define ADDRESS_DECODE_MASK 8'hf0
`define SPI_MASTER_VERSION_REG 8'h00
`define SPI_MASTER_CONTROL_REG 8'h01
`define TRANS_TYPE_REG 8'h02
`define TRANS_CTRL_REG 8'h03
`define TRANS_STS_REG 8'h04
`define TRANS_ERROR_REG 8'h05
`define DIRECT_ACCESS_DATA_REG 8'h06
`define SD_ADDR_7_0_REG 8'h07
`define SD_ADDR_15_8_REG 8'h08
`define SD_ADDR_23_16_REG 8'h09
`define SD_ADDR_31_24_REG 8'h0a
`define SPI_CLK_DEL_REG 8'h0b
 
 
//FifoAddresses
`define FIFO_DATA_REG 3'b000
`define FIFO_STATUS_REG 3'b001
`define FIFO_DATA_COUNT_MSB 3'b010
`define FIFO_DATA_COUNT_LSB 3'b011
`define FIFO_CONTROL_REG 3'b100
 
 
`ifdef SIM_COMPILE
`define SLOW_SPI_CLK 8'h2
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h001
`define TWO_FIFTY_MS 12'h001
`define ONE_HUNDRED_MS 12'h00c
`else //not SIM_COMPILE
 
`ifdef SPI_SYS_CLK_48MHZ
 
// --------------- spiSysClk = 48MHz
// if you change the clock frequency you will need to change these constants
 
// SLOW_SPI_CLK controls the SPI clock at start up.
// should be aiming for 400KHz
// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1
`define SLOW_SPI_CLK 8'h3b
// controls the SPI clock after init is complete.
// should be aiming for 24MHz ?
// controls the SPI clock after init is complete.
// should be aiming for 24MHz ?
// if spiSysClk >= 48MHz
// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1
// else FAST_SPI_CLK = 0
`define FAST_SPI_CLK 8'h00
// TWO_MS = ((2mS * spiSysClk) / 256) - 1
`define TWO_MS 10'h177
// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1
`define TWO_FIFTY_MS 12'h0b6
// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1
`define ONE_HUNDRED_MS 12'h048
 
`else //not SPI_SYS_CLK_48MHZ
 
`ifdef SPI_SYS_CLK_30MHZ
// --------------- spiSysClk = 30MHz
`define SLOW_SPI_CLK 8'h24
`define FAST_SPI_CLK 8'h00
`define TWO_MS 10'h0e9
`define TWO_FIFTY_MS 12'h071
`define ONE_HUNDRED_MS 12'h02c
 
`endif //SPI_SYS_CLK_30MHZ
`endif //SPI_SYS_CLK_48MHZ
`endif //SIM_COMPILE
 
 
 
`ifdef SIM_COMPILE
`define SD_INIT_START_SEQ_LEN 8'h03
`define MAX_8_BIT 8'h08
`else
`define SD_INIT_START_SEQ_LEN 8'ha0
`define MAX_8_BIT 8'hff
`endif
 
 
`define WR_RESP_TOUT 12'hf00
 
`define NO_BLOCK_REQ 2'b00
`define WRITE_SD_BLOCK 2'b01
`define READ_SD_BLOCK 2'b10
 
`define READ_NO_ERROR 2'b00
`define READ_CMD_ERROR 2'b01
`define READ_TOKEN_ERROR 2'b10
 
`define WRITE_NO_ERROR 2'b00
`define WRITE_CMD_ERROR 2'b01
`define WRITE_DATA_ERROR 2'b10
`define WRITE_BUSY_ERROR 2'b11
 
 
`define TRANS_NOT_BUSY 1'b0
`define TRANS_BUSY 1'b1
 
`define TRANS_START 1'b1
`define TRANS_STOP 1'b0
 
`define DIRECT_ACCESS 2'b00
`define INIT_SD 2'b01
`define RW_READ_SD_BLOCK 2'b10
`define RW_WRITE_SD_BLOCK 2'b11
 
`define INIT_NO_ERROR 2'b00
`define INIT_CMD0_ERROR 2'b01
`define INIT_CMD1_ERROR 2'b10
 
`define TX_FIFO_DEPTH 512
`define TX_FIFO_ADDR_WIDTH 9
`define RX_FIFO_DEPTH 512
`define RX_FIFO_ADDR_WIDTH 9
 

Line No.	Rev	Author	Line
1	2	sfielding	`// ------------------------ spiMaster_defines.v ----------------------`
2			`// Version 0.0 - April 2008. Created`
3			`// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and`
4			`// spiSysClk. Fixed bug in bus accessible reset. Changed names of`
5			`// fifo related modules to avoid conflict with other IP cores.`
6			`// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug`
7			`// in wb_ack. Fixed file headers, and added description`
8
9			`define SPI_MASTER_VERSION_NUM 8'h11
10			`define SPI_SYS_CLK_48MHZ
11			//`define SPI_SYS_CLK_30MHZ
12
13			`//memoryMap`
14			`define CTRL_STS_REG_BASE 8'h00
15			`define RX_FIFO_BASE 8'h10
16			`define TX_FIFO_BASE 8'h20
17			`define ADDRESS_DECODE_MASK 8'hf0
18			`define SPI_MASTER_VERSION_REG 8'h00
19			`define SPI_MASTER_CONTROL_REG 8'h01
20			`define TRANS_TYPE_REG 8'h02
21			`define TRANS_CTRL_REG 8'h03
22			`define TRANS_STS_REG 8'h04
23			`define TRANS_ERROR_REG 8'h05
24			`define DIRECT_ACCESS_DATA_REG 8'h06
25			`define SD_ADDR_7_0_REG 8'h07
26			`define SD_ADDR_15_8_REG 8'h08
27			`define SD_ADDR_23_16_REG 8'h09
28			`define SD_ADDR_31_24_REG 8'h0a
29			`define SPI_CLK_DEL_REG 8'h0b
30
31
32			`//FifoAddresses`
33			`define FIFO_DATA_REG 3'b000
34			`define FIFO_STATUS_REG 3'b001
35			`define FIFO_DATA_COUNT_MSB 3'b010
36			`define FIFO_DATA_COUNT_LSB 3'b011
37			`define FIFO_CONTROL_REG 3'b100
38
39
40			`ifdef SIM_COMPILE
41			`define SLOW_SPI_CLK 8'h2
42			`define FAST_SPI_CLK 8'h00
43			`define TWO_MS 10'h001
44			`define TWO_FIFTY_MS 12'h001
45			`define ONE_HUNDRED_MS 12'h00c
46			`else //not SIM_COMPILE
47
48			`ifdef SPI_SYS_CLK_48MHZ
49
50			`// --------------- spiSysClk = 48MHz`
51			`// if you change the clock frequency you will need to change these constants`
52
53			`// SLOW_SPI_CLK controls the SPI clock at start up.`
54			`// should be aiming for 400KHz`
55			`// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1`
56			`define SLOW_SPI_CLK 8'h3b
57			`// controls the SPI clock after init is complete.`
58			`// should be aiming for 24MHz ?`
59			`// controls the SPI clock after init is complete.`
60			`// should be aiming for 24MHz ?`
61			`// if spiSysClk >= 48MHz`
62			`// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1`
63			`// else FAST_SPI_CLK = 0`
64			`define FAST_SPI_CLK 8'h00
65			`// TWO_MS = ((2mS * spiSysClk) / 256) - 1`
66			`define TWO_MS 10'h177
67			`// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1`
68			`define TWO_FIFTY_MS 12'h0b6
69			`// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1`
70			`define ONE_HUNDRED_MS 12'h048
71
72			`else //not SPI_SYS_CLK_48MHZ
73
74			`ifdef SPI_SYS_CLK_30MHZ
75			`// --------------- spiSysClk = 30MHz`
76			`define SLOW_SPI_CLK 8'h24
77			`define FAST_SPI_CLK 8'h00
78			`define TWO_MS 10'h0e9
79			`define TWO_FIFTY_MS 12'h071
80			`define ONE_HUNDRED_MS 12'h02c
81
82			`endif //SPI_SYS_CLK_30MHZ
83			`endif //SPI_SYS_CLK_48MHZ
84			`endif //SIM_COMPILE
85
86
87
88			`ifdef SIM_COMPILE
89			`define SD_INIT_START_SEQ_LEN 8'h03
90			`define MAX_8_BIT 8'h08
91			`else
92			`define SD_INIT_START_SEQ_LEN 8'ha0
93			`define MAX_8_BIT 8'hff
94			`endif
95
96
97			`define WR_RESP_TOUT 12'hf00
98
99			`define NO_BLOCK_REQ 2'b00
100			`define WRITE_SD_BLOCK 2'b01
101			`define READ_SD_BLOCK 2'b10
102
103			`define READ_NO_ERROR 2'b00
104			`define READ_CMD_ERROR 2'b01
105			`define READ_TOKEN_ERROR 2'b10
106
107			`define WRITE_NO_ERROR 2'b00
108			`define WRITE_CMD_ERROR 2'b01
109			`define WRITE_DATA_ERROR 2'b10
110			`define WRITE_BUSY_ERROR 2'b11
111
112
113			`define TRANS_NOT_BUSY 1'b0
114			`define TRANS_BUSY 1'b1
115
116			`define TRANS_START 1'b1
117			`define TRANS_STOP 1'b0
118
119			`define DIRECT_ACCESS 2'b00
120			`define INIT_SD 2'b01
121			`define RW_READ_SD_BLOCK 2'b10
122			`define RW_WRITE_SD_BLOCK 2'b11
123
124			`define INIT_NO_ERROR 2'b00
125			`define INIT_CMD0_ERROR 2'b01
126			`define INIT_CMD1_ERROR 2'b10
127
128			`define TX_FIFO_DEPTH 512
129			`define TX_FIFO_ADDR_WIDTH 9
130			`define RX_FIFO_DEPTH 512
131			`define RX_FIFO_ADDR_WIDTH 9
132

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[/] [spimaster/] [trunk/] [RTL/] [spiMaster_defines.v] - Blame information for rev 2