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[/] [spimaster/] [trunk/] [model/] [sdModel.v] - Blame information for rev 4

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1 2 sfielding 
`include "timescale.v"
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module sdModel(
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  spiClk,
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  spiDataIn,
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  spiDataOut,
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  spiCS_n
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);
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input spiClk;
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input spiDataIn;
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output spiDataOut;
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reg spiDataOut;
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input spiCS_n;
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//local wires and regs
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reg [7:0] rxByte;
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reg [7:0] respByte;
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reg [1:0] smSt;
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reg [7:0] cnt;
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`define START 2'b00
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`define WAIT_FF 2'b01
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`define WAIT_FF_FIN 2'b10
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initial
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begin
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  smSt = `START;
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end
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// ------------------------------ txRxByte --------------------------
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task txRxByte;
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input [7:0] txData;
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output [7:0] rxData;
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integer i;
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begin
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  spiDataOut <= txData[7];
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  //@(negedge spiCS_n);
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  for (i=0;i<=7;i=i+1) begin
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    @(posedge spiClk);
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    rxData[0] <= spiDataIn;
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    rxData = rxData << 1;
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    @(negedge spiClk);
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    spiDataOut <= txData[6];
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    txData = txData << 1;
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  end
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end
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endtask
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//response state machine
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always begin
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    case (smSt)
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      `START: begin
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        txRxByte(8'hff, rxByte);
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        if (rxByte == 8'hff) begin
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          smSt <= `WAIT_FF;
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          cnt <= 8'h00;
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        end
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      end
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      `WAIT_FF: begin
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        txRxByte(8'hff, rxByte);
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        if (rxByte == 8'hff) begin
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          cnt <= cnt + 1'b1;
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          if (cnt == 8'h04) begin
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            txRxByte(respByte, rxByte);
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            smSt <= `WAIT_FF_FIN;
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          end
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        end
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        else begin
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          smSt <= `START;
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          cnt <= 8'h00;
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        end
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      end
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      `WAIT_FF_FIN: begin
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        txRxByte(8'hff, rxByte);
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        if (rxByte == 8'h04) begin
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          cnt <= cnt + 1'b1;
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          if (cnt == 8'hff) begin
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            txRxByte(respByte, rxByte);
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            smSt <= `START;
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          end
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        end
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        else
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          smSt <= `START;
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      end
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    endcase
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end
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// setRespByte
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task setRespByte;
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  input [7:0] dataByte;
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  begin
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    respByte = dataByte;
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  end
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endtask
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endmodule

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