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sfielding |
# Copyright (C) 1991-2007 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# spiMaster_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20Q240C8
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set_global_assignment -name TOP_LEVEL_ENTITY spiMaster
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:03:18 FEBRUARY 21, 2008"
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set_global_assignment -name LAST_QUARTUS_VERSION 7.2
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
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set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBus_h.v
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set_global_assignment -name VERILOG_FILE ../rtl/ctrlStsRegBI.v
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set_global_assignment -name VERILOG_FILE ../rtl/dpMem_dc.v
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set_global_assignment -name VERILOG_FILE ../rtl/fifoRTL.v
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set_global_assignment -name VERILOG_FILE ../rtl/initSD.v
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set_global_assignment -name VERILOG_FILE ../rtl/readWriteSDBlock.v
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set_global_assignment -name VERILOG_FILE ../rtl/readWriteSPIWireData.v
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set_global_assignment -name VERILOG_FILE ../rtl/RxFifo.v
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set_global_assignment -name VERILOG_FILE ../rtl/RxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../rtl/sendCmd.v
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set_global_assignment -name VERILOG_FILE ../rtl/spiCtrl.v
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set_global_assignment -name VERILOG_FILE ../rtl/spiMaster.v
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set_global_assignment -name VERILOG_FILE ../rtl/spiMaster_h.v
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set_global_assignment -name VERILOG_FILE ../rtl/spiTxRxData.v
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set_global_assignment -name VERILOG_FILE ../rtl/timescale.v
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set_global_assignment -name VERILOG_FILE ../rtl/TxFifo.v
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set_global_assignment -name VERILOG_FILE ../rtl/TxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBI.v
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set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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