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[/] [sport/] [trunk/] [bench/] [testbench_top.v] - Blame information for rev 2

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1 2 jeaander 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  weigand_tx_top.v                                            ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the Time Triggered Protocol Controller ////
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////  http://www.opencores.org/projects/weigand/                  ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Jeff Anderson                                          ////
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////       jeaander@opencores.org                                 ////
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////                                                              ////
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////                                                              ////
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////  All additional information is available in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2013 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//// The Weigand protocol is maintained by                        ////
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//// This product has been tested to interoperate with certified  ////
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//// devices, but has not been certified itself.  This product    ////
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//// should be certified through prior to claiming strict         ////
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//// adherence to the standard.                                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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//  Revisions at end of file
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//
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`include "timescale.v"
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`include "SPORT_defines.v"
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module testbench_top;
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  reg [5:0]   wb_addr_i;
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  reg [31:0]  wb_dat_i;
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  wire [31:0] wb_dat_o;
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  wire [31:0] wb_dat_o_rx;
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  reg         wb_cyc_i;
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  reg         wb_stb_i;
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  reg [2:0]   wb_cti_i;
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  reg [3:0]   wb_sel_i;
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  reg         wb_we_i;
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  reg         wb_rst_i;
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  reg         wb_clk_i;
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  reg         one_i, zero_i;
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  //DUTs
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  sport_top sport_top(wb_clk_i,wb_rst_i,wb_dat_i,wb_dat_o,wb_cyc_i,wb_stb_i,wb_cti_i,wb_sel_i,wb_we_i,wb_addr_i,
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                      wb_ack_o,wb_err_o,wb_rty_o, DTxPRI,DTxSEC,TSCLKx,TFSx,DRxPRI,DRxSEC,RSCLKx,TRSx,);
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  //tasks for simulation
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  initial begin
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    wb_addr_i = 6'h0;
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    wb_dat_i = 32'h0;
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    wb_cyc_i = 1'b0;
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    wb_stb_i = 1'b0;
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    wb_we_i = 1'b0;
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    wb_rst_i = 1'b0;
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    wb_clk_i = 1'b0;
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    one_i = 1'b1;
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    zero_i = 1'b1;
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  end
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  always
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    #5 wb_clk_i = !wb_clk_i;
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  /**********************   tasks run by testcases for this testbench ******************/
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  //SPORT bus write tasks
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  task SPORT_write;
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    input [63:0] SPORT_data;
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    input [5:0]  word_length;
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    input [5:0]  p2p;
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    input [5:0]  pw;
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    integer i;
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    integer j;
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    begin
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      j = 0;
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      repeat (word_length) begin
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        @ (posedge wb_clk_i) begin
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          if (SPORT_data[j] == 1'b0) begin
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            SPORT0(pw);
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          end
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          else begin
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            SPORT1(pw);
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          end
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          j=j+1;
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          i = 0;
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          while(i <= p2p) begin
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            @ (posedge wb_clk_i) begin i=i+1; end
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          end
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        end
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      end
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    end
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  endtask
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  task SPORT0;
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    input [5:0] pw;
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    integer i;
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    begin
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      for (i = 0; i <= pw; i=i+1) begin
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        @(posedge wb_clk_i)  zero_i = 1'b0;
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      end
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      zero_i = 1'b1;
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    end
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  endtask
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  task SPORT1;
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    input [5:0] pw;
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    integer i;
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    begin
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      for (i = 0; i <= pw; i=i+1) begin
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        @(posedge wb_clk_i)  one_i = 1'b0;
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      end
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      one_i = 1'b1;
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    end
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  endtask
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  //Wishbone readn adn write tasks
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  task wb_rst;
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    begin
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          wb_rst_i = 1'b1;
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      #20 wb_rst_i = 1'b0;
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    end
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  endtask
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  task wb_write_async;
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    input [31:0] wb_data;
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    begin
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = `SPORT_ADDR;
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        wb_dat_i = wb_data;
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b1;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = 6'h0;
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        wb_dat_i = 32'h0;
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        wb_stb_i = 1'b0;
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        wb_cyc_i = 1'b0;
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        wb_we_i = 1'b0;
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      end
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    end
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  endtask
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  task wb_write_sync;
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    input [31:0] wb_data;
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    begin
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = `SPORT_ADDR;
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        wb_dat_i = wb_data;
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b1;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = `SPORT_ADDR;
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        wb_dat_i = wb_data;
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b1;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = 6'h0;
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        wb_dat_i = 32'h0;
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        wb_stb_i = 1'b0;
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        wb_cyc_i = 1'b0;
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        wb_we_i = 1'b0;
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      end
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    end
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  endtask
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  task wb_writep2p_async;
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    input [31:0] p2p;
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    begin
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = `WB_CNFG_RX;
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        wb_dat_i = p2p;
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b1;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = 6'h0;
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        wb_dat_i = 32'h0;
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        wb_stb_i = 1'b0;
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        wb_cyc_i = 1'b0;
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        wb_we_i = 1'b0;
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      end
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    end
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  endtask
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  task wb_writepw_async;
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    input [31:0] pw;
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    begin
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = `WB_CNFG_TX;
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        wb_dat_i = pw;
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b1;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_addr_i = 6'h0;
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        wb_dat_i = 32'h0;
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        wb_stb_i = 1'b0;
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        wb_cyc_i = 1'b0;
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        wb_we_i = 1'b0;
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      end
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    end
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  endtask
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  task wb_read_async;
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    begin
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      @ (posedge wb_clk_i) begin
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b0;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_stb_i = 1'b0;
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        wb_cyc_i = 1'b0;
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      end
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    end
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  endtask
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  task wb_read_sync;
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    begin
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      @ (posedge wb_clk_i) begin
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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        wb_we_i = 1'b0;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_stb_i = 1'b1;
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        wb_cyc_i = 1'b1;
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      end
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      @ (posedge wb_clk_i) begin
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        wb_stb_i = 1'b0;
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        wb_cyc_i = 1'b0;
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      end
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    end
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  endtask
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endmodule

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