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[/] [sport/] [trunk/] [rtl/] [verilog/] [sport_defines.v] - Blame information for rev 4

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SPORT_defines.v                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the SPORT Controller                 ////
////  http://www.opencores.org/projects/SPORT/                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////       Jeff Anderson                                          ////
////       jeaander@opencores.org                                 ////
////                                                              ////
////                                                              ////
////  All additional information is available in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2013 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//  Revisions at end of file
//
 
/**********************  WISHBONE DEFINES  ***************************/
// define the WB bus width; uncomment ONE correct width
//`define WB_WIDTH64
`define WB_WIDTH32
//`define WB_WIDTH16
//`define WB_WIDTH08
 
 
`ifdef WB_WIDTH64
  `define WB_WIDTH 64
  `define SPORT_WIDTH64
`elsif WB_WIDTH32
  `define WB_WIDTH 32
  `define SPORT_WIDTH32
`elsif WB_WIDTH16
  `define WB_WIDTH 16
  `define SPORT_WIDTH16
`else
  `define WB_WIDTH 8
  `define SPORT_WIDTH8
`endif
 
//define the width of WB address
`define WB_ADDR_WIDTH 6
 
/*********************** SPORT DEFINES *****************************/
//SPORT_WIDTH defined above
 
//define depth of FIFO 
`define SPORT_FIFODEPTH 10
 
//uncomment a single implementation of FIFO;
`define SPORT_CUSTOMFIFO
//`define SPORT_XILINX
//`define SPORT_ALTERA
 
//set to base address of controller; base address is data FIFO, and the config registers are relative to it
`define SPORT_ADDR 6'h01
`define SPORT_ADDR_MASK 6'h20
 
`define WB_CNFG_RX `SPORT_ADDR+1
`define WB_CNFG_TX `SPORT_ADDR+2
 
`define RESET 3'h0
`define IDLE  3'h1
`define FS    3'h3
`define RX    3'h2
`define TX    3'h2
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: $
//

Line No.	Rev	Author	Line
1	4	jeaander	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SPORT_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SPORT Controller ////`
7			`//// http://www.opencores.org/projects/SPORT/ ////`
8			`//// ////`
9			`//// ////`
10			`//// Author(s): ////`
11			`//// Jeff Anderson ////`
12			`//// jeaander@opencores.org ////`
13			`//// ////`
14			`//// ////`
15			`//// All additional information is available in the README.txt ////`
16			`//// file. ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2013 Authors ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// Revisions at end of file`
47			`//`
48
49			`/******************** WISHBONE DEFINES *************************/`
50			`// define the WB bus width; uncomment ONE correct width`
51			//`define WB_WIDTH64
52			`define WB_WIDTH32
53			//`define WB_WIDTH16
54			//`define WB_WIDTH08
55
56
57			`ifdef WB_WIDTH64
58			`define WB_WIDTH 64
59			`define SPORT_WIDTH64
60			`elsif WB_WIDTH32
61			`define WB_WIDTH 32
62			`define SPORT_WIDTH32
63			`elsif WB_WIDTH16
64			`define WB_WIDTH 16
65			`define SPORT_WIDTH16
66			`else
67			`define WB_WIDTH 8
68			`define SPORT_WIDTH8
69			`endif
70
71			`//define the width of WB address`
72			`define WB_ADDR_WIDTH 6
73
74			`/********************* SPORT DEFINES ***************************/`
75			`//SPORT_WIDTH defined above`
76
77			`//define depth of FIFO`
78			`define SPORT_FIFODEPTH 10
79
80			`//uncomment a single implementation of FIFO;`
81			`define SPORT_CUSTOMFIFO
82			//`define SPORT_XILINX
83			//`define SPORT_ALTERA
84
85			`//set to base address of controller; base address is data FIFO, and the config registers are relative to it`
86			`define SPORT_ADDR 6'h01
87			`define SPORT_ADDR_MASK 6'h20
88
89			`define WB_CNFG_RX `SPORT_ADDR+1
90			`define WB_CNFG_TX `SPORT_ADDR+2
91
92			`define RESET 3'h0
93			`define IDLE 3'h1
94			`define FS 3'h3
95			`define RX 3'h2
96			`define TX 3'h2
97			`//////////////////////////////////////////////////////////////////////`
98			`//`
99			`// CVS Revision History`
100			`//`
101			`// $Log: $`
102			`//`

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[/] [sport/] [trunk/] [rtl/] [verilog/] [sport_defines.v] - Blame information for rev 4